On Tue, Oct 24, 2023 at 4:13 PM Andrew Lunn <andrew@xxxxxxx> wrote: > > > Yes, I'll add more detailed comments to the code in the v2. The calibration > > procedure itself targets the PSGMII device, which is internal to the SoC and can > > be logically accessed as a PHY device on the MDIO bus. This component is a > > little opaque and has some nonstandard MII register definitions. > > > > The "testing" phase that follows the calibration accesses both the internal > > QCA8K switch ports and the external QCA8075 PHY. For example, it puts both the > > switch ports and the PHY ports in loopback before starting packet generation on > > the external PHYs. This is done to verify that the PSGMII link works correctly > > after being calibrated. > > > > So this code interacts with both internal ESS devices and external PHYs, but > > mostly the former, which is why I kept everything in the MAC/switch driver. > > Accessing the external PHYs i would suggest go over the normal phylib > API. Somebody might build a board using a different PHY, with > different registers. If all you need is loopback, there is a phylib > call for that. > > Directly accessing the internal ESS is fine, it cannot be changed, but > if there are phylib helpers which do the same thing, consider using > them. Hi, This SoC is a bit special as it only supports using RGMII and PSGMII. PSGMII is Qualcomm-s modification of SGMII with 5 SGMII lines to provide 1G of bandwidth from the switch to PHY-s. However, PSGMII is also weird in the sense that it requires calibration to be carried on each boot, as otherwise packet loss will start to occur. But for calibration to work, you must enable loopback on the switch ports and on the PHY-s, both loopback and CRC verification must be enabled. Then you can actually enable the PSGMII serdes calibration in the SoC but it must occur on all of the PHYs at the same time, hence why broadcast is used. As far as the PHY-s go, there are only 2 PHY models supporting PSGMII, QCA8072 and QCA8075, both from Qualcomm, and differing only in the number of ports. QCA8072 has 2 ports while QCA8075 has 5 ports. Each of them also has a serdes PHY exposed over MDIO. These PHY-s are still being used in IPQ8074 and IPQ6018 802.11ax SoC-s. So in a nutshell, this is how stuff is connected (To the best of my knowledge): https://asciiflow.com/#/share/eJzVVktuwjAQvYrlFUggwk9p2fGHBVVoVAmkbAJxRSTjoGDUIMQtKg5T9TScpG4T8iEOARLaYs3iZTx%2B9oxnMt5Aos4RrJEVxjmI1TUyYQ1uFGgpsPZYKeUUuGaoJIoMUWRR9qFA4I79%2B%2BeloigksB606QyZBFFXE7JoGoSaBsbIjLIIDp5Fpi8N27KcjbaI5UjkKY%2FT0fUJZQFQMW%2Bu2J3olDfRYTcGWqsFRta5%2B8TqAufffVzh8q0l8tI8fBodLwoRSoZJgeDDRYZ%2BQAkcUNmbrXiwai8aGJr%2BqiMt9aOCxkrHNK%2BTcG43pZfsYUGxG4scZg8PVyqeGvN5%2BmceNusP5bL4lLSWflmA%2FKbT6SxUMbzoxEfkH9NcEJXdjfURUzH%2FaQAkuTvo94HUGxfk9nOrLXPDE0tTtWye6UwlBOElP8qxNJk6XhqAcWgYLcHzN2X2CpozRoKr%2FCPhJHCk1rlWd%2FJ8chtflnj3ILZT3LTZX%2FN7PoqWW0j%2BNrh3Ol7RRSe6IBuHRhgklpGpsWLwt519fKvyQ9BbT0xdC524N3bdahqLBXsgMnga%2BQw5WefrhOkEmzkxtTc0TLcjCmKpUE1vC0EQGuoS5UeFoxc1i0%2F6u3RGgTtITNzRJ%2FbD3tHwi%2FfORYFbuP0C5MQClA%3D%3D) Sorry for the external link, but I cannot get the ASCII diagram to show properly via plain-text. Regards, Robert > Andrew -- Robert Marko Staff Embedded Linux Engineer Sartura Ltd. Lendavska ulica 16a 10000 Zagreb, Croatia Email: robert.marko@xxxxxxxxxx Web: www.sartura.hr
