> Yes, I'll add more detailed comments to the code in the v2. The calibration
> procedure itself targets the PSGMII device, which is internal to the SoC and can
> be logically accessed as a PHY device on the MDIO bus. This component is a
> little opaque and has some nonstandard MII register definitions.
>
> The "testing" phase that follows the calibration accesses both the internal
> QCA8K switch ports and the external QCA8075 PHY. For example, it puts both the
> switch ports and the PHY ports in loopback before starting packet generation on
> the external PHYs. This is done to verify that the PSGMII link works correctly
> after being calibrated.
>
> So this code interacts with both internal ESS devices and external PHYs, but
> mostly the former, which is why I kept everything in the MAC/switch driver.
Accessing the external PHYs i would suggest go over the normal phylib
API. Somebody might build a board using a different PHY, with
different registers. If all you need is loopback, there is a phylib
call for that.
Directly accessing the internal ESS is fine, it cannot be changed, but
if there are phylib helpers which do the same thing, consider using
them.
Andrew
