> + ret = oa_tc6_perform_ctrl(tc6, RESET, ®val, 1, true, true); > + ret = oa_tc6_perform_ctrl(tc6, RESET, ®val, 1, true, false); Just looking at this, it is not clear what these true/false mean. Maybe add some #defines #define TC6_READ true #define TC6_WRITE false #define TC6_PROTECTED true #define TC6_UNPROTECTED false > + if (ret) > + return ret; > + > + /* The chip completes a reset in 3us, we might get here earlier than > + * that, as an added margin we'll conditionally sleep 5us. > + */ > + udelay(5); > + > + ret = oa_tc6_perform_ctrl(tc6, STATUS0, ®val, 1, false, false); > + if (ret) > + return ret; > + > + /* Check for reset complete interrupt status */ > + if (regval & RESETC) { > + regval = RESETC; People don't always agree, but i found STATUS0_RESETC easier to see you have the correct bit for the register you just read. Andrew