On Mon, Oct 23, 2023 at 08:40:51AM +0800, Yu Chien Peter Lin wrote: > Add "andestech,cpu-intc" compatible string which indicates that > Andes specific local interrupt is supported on the core, > e.g. AX45MP cores have 3 types of non-standard local interrupt > can be handled in supervisor mode: > > - Slave port ECC error interrupt > - Bus write transaction error interrupt > - Performance monitor overflow interrupt > > These interrupts are enabled/disabled via a custom register > SLIE instead of the standard interrupt enable register SIE. > > Signed-off-by: Yu Chien Peter Lin <peterlin@xxxxxxxxxxxxx> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Updated commit message > - Fixed possible compatibles for Andes INTC > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..4c1bbcf07406 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -99,7 +99,12 @@ properties: > const: 1 > > compatible: > - const: riscv,cpu-intc > + oneOf: > + - items: > + - enum: > + - andestech,cpu-intc Why is this an enum rather than const? What other entries are we going to add here in the near future? > + - const: riscv,cpu-intc My follow-up question, if my original question on the v2 series had been answered was going to be about how generic the "andestech,cpu-intc" compatible is. Having a cpu-specific compatible in addition to "andestech,cpu-intc" one makes sense to me, so that we can differentiate between implementations/integrations of this intc, especially if Andes have no plans to move to the standard implementation. Cheers, Conor. > + - const: riscv,cpu-intc > > interrupt-controller: true > > -- > 2.34.1 >
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