Hi All, This patch series introduces the Andes PMU extension, which serves the same purpose as Sscofpmf. In this version we use FDT-based probing and the CONFIG_ANDES_CUSTOM_PMU to enable perf sampling and filtering support. Its non-standard local interrupt is assigned to bit 18 in the custom S-mode local interrupt enable/pending registers (slie/slip), while the interrupt cause is (256 + 18). The feature needs the PMU device registered in OpenSBI. The OpenSBI and Linux patches can be found on Andes Technology GitHub - https://github.com/andestech/opensbi/commits/andes-pmu-support-v2 - https://github.com/andestech/linux/commits/andes-pmu-support-v3 The PMU device tree node used on AX45MP: - https://github.com/andestech/opensbi/blob/andes-pmu-support-v2/docs/pmu_support.md#example-3 Tested hardware: - ASUS Tinker-V (RZ/Five, AX45MP single core) - Andes AE350 (AX45MP quad core) Locus Wei-Han Chen (1): riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin (12): riscv: errata: Rename defines for Andes irqchip/riscv-intc: Allow large non-standard hwirq number irqchip/riscv-intc: Introduce Andes IRQ chip dt-bindings: riscv: Add Andes interrupt controller compatible string riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC perf: RISC-V: Eliminate redundant IRQ enable/disable operations RISC-V: Move T-Head PMU to CPU feature alternative framework perf: RISC-V: Introduce Andes PMU for perf event sampling dt-bindings: riscv: Add T-Head PMU extension description dt-bindings: riscv: Add Andes PMU extension description riscv: dts: allwinner: Add T-Head PMU extension riscv: dts: renesas: Add Andes PMU extension .../devicetree/bindings/riscv/cpus.yaml | 7 +- .../devicetree/bindings/riscv/extensions.yaml | 13 ++ arch/riscv/Kconfig.errata | 13 -- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/errata/andes/errata.c | 10 +- arch/riscv/errata/thead/errata.c | 19 --- arch/riscv/include/asm/errata_list.h | 19 +-- arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- arch/riscv/kernel/cpufeature.c | 2 + drivers/irqchip/irq-riscv-intc.c | 63 +++++++-- drivers/perf/Kconfig | 27 ++++ drivers/perf/riscv_pmu_sbi.c | 51 +++++-- include/linux/irqchip/irq-riscv-intc.h | 12 ++ .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 21 files changed, 499 insertions(+), 79 deletions(-) create mode 100644 include/linux/irqchip/irq-riscv-intc.h create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json -- 2.34.1
