> -----Original Message-----
> From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: linux-rockchip@xxxxxxxxxxxxxxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> linux-pm@xxxxxxxxxxxxxxx; Heiko Stuebner <heiko@xxxxxxxxx>; Chanwoo Choi
> <chanwoo@xxxxxxxxxx>; Kyungmin Park <kyungmin.park@xxxxxxxxxxx>; MyungJoo
> Ham <myungjoo.ham@xxxxxxxxxxx>; Will Deacon <will@xxxxxxxxxx>; Mark
> Rutland <mark.rutland@xxxxxxx>; kernel@xxxxxxxxxxxxxx; Michael Riesch
> <michael.riesch@xxxxxxxxxxxxxx>; Robin Murphy <robin.murphy@xxxxxxx>;
> Vincent Legoll <vincent.legoll@xxxxxxxxx>; Rob Herring
> <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>;
> devicetree@xxxxxxxxxxxxxxx; Sebastian Reichel
> <sebastian.reichel@xxxxxxxxxxxxx>; Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>;
> Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
> Subject: [PATCH v8 08/26] PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE
> defines
>
> The DDRTYPE defines are named to be RK3399 specific, but they can be used
> for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_ prefix with
> ROCKCHIP_. They are defined in a SoC specific header file, so when
> generalizing the prefix also move the new defines to a SoC agnostic header
> file. While at it use GENMASK to define the DDRTYPE bitfield and give it a
> name including the full register name.
>
> Reviewed-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
> Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 9 +++++----
> drivers/devfreq/rk3399_dmc.c | 10 +++++-----
> include/soc/rockchip/rk3399_grf.h | 7 +------
> include/soc/rockchip/rockchip_grf.h | 17 +++++++++++++++++
> 4 files changed, 28 insertions(+), 15 deletions(-) create mode 100644
> include/soc/rockchip/rockchip_grf.h
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index 28c18bbf6baa5..82d18c60538a5 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -18,8 +18,10 @@
> #include <linux/list.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/bitfield.h>
> #include <linux/bits.h>
>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
>
> #define DMC_MAX_CHANNELS 2
> @@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct
> devfreq_event_dev *edev)
> writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> - if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
> + if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
> - else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
> + else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
>
> /* enable count, use software mode */
> @@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
>
> /* get ddr type */
> regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> dfi->channel_mask = GENMASK(1, 0);
> dfi->max_channels = 2;
> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
> index daff407026157..fd2c5ffedf41e 100644
> --- a/drivers/devfreq/rk3399_dmc.c
> +++ b/drivers/devfreq/rk3399_dmc.c
> @@ -22,6 +22,7 @@
> #include <linux/suspend.h>
>
> #include <soc/rockchip/pm_domains.h>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> #include <soc/rockchip/rockchip_sip.h>
>
> @@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct
> platform_device *pdev)
> }
>
> regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> switch (ddr_type) {
> - case RK3399_PMUGRF_DDRTYPE_DDR3:
> + case ROCKCHIP_DDRTYPE_DDR3:
> data->odt_dis_freq = data->ddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR3:
> + case ROCKCHIP_DDRTYPE_LPDDR3:
> data->odt_dis_freq = data->lpddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR4:
> + case ROCKCHIP_DDRTYPE_LPDDR4:
> data->odt_dis_freq = data->lpddr4_odt_dis_freq;
> break;
> default:
> diff --git a/include/soc/rockchip/rk3399_grf.h
> b/include/soc/rockchip/rk3399_grf.h
> index 3eebabcb28123..775f8444bea8d 100644
> --- a/include/soc/rockchip/rk3399_grf.h
> +++ b/include/soc/rockchip/rk3399_grf.h
> @@ -11,11 +11,6 @@
>
> /* PMU GRF Registers */
> #define RK3399_PMUGRF_OS_REG2 0x308
> -#define RK3399_PMUGRF_DDRTYPE_SHIFT 13
> -#define RK3399_PMUGRF_DDRTYPE_MASK 7
> -#define RK3399_PMUGRF_DDRTYPE_DDR3 3
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7
> +#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
>
> #endif
> diff --git a/include/soc/rockchip/rockchip_grf.h
> b/include/soc/rockchip/rockchip_grf.h
> new file mode 100644
> index 0000000000000..dde1a9796ccb5
> --- /dev/null
> +++ b/include/soc/rockchip/rockchip_grf.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Rockchip General Register Files definitions */
> +
> +#ifndef __SOC_ROCKCHIP_GRF_H
> +#define __SOC_ROCKCHIP_GRF_H
> +
> +/* Rockchip DDRTYPE defines */
> +enum {
> + ROCKCHIP_DDRTYPE_DDR3 = 3,
> + ROCKCHIP_DDRTYPE_LPDDR2 = 5,
> + ROCKCHIP_DDRTYPE_LPDDR3 = 6,
> + ROCKCHIP_DDRTYPE_LPDDR4 = 7,
> +};
> +
> +#endif /* __SOC_ROCKCHIP_GRF_H */
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
