On 13/10/2023 17:07, Conor Dooley wrote: >>> +maintainers: >>> + - Kris Chaplin <kris.chaplin@xxxxxxx> >>> + >>> +properties: >>> + compatible: >>> + const: amd,axi-1wire-master >> >> That's a quite generic compatible. axi is ARM term, 1-wire is the name >> of the bus and master is the role. Concatenating three common words does >> not create unique device name. Compatibles are supposed to be specific >> and this is really relaxed. Anything can be over AXI, everything in >> 1wire is 1wire and every master device is a master. > > Given the vendor (and the title of the binding) this is almost certainly > an FPGA IP core, so the generic name is understandable. Using the exact > name of the IP in the AMD/Xilinx catalog probably is the best choice? Other option is that it is a part of some Zynq SoC. Best regards, Krzysztof
