On Mon, Sep 25, 2023 at 06:10:15PM +0300, Laurentiu Tudor wrote: > Wrap the usb controllers in an intermediate simple-bus and use it to > constrain the dma address size of these usb controllers to the 40b > that they generate toward the interconnect. This is required because > the SoC uses 48b address sizes and this mismatch would lead to smmu > context faults [1] because the usb generates 40b addresses while the > smmu page tables are populated with 48b wide addresses. > > [1] > xhci-hcd xhci-hcd.0.auto: xHCI Host Controller > xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 > xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x0000000002000010 > xhci-hcd xhci-hcd.0.auto: irq 108, io mem 0x03100000 > xhci-hcd xhci-hcd.0.auto: xHCI Host Controller > xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 > xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed > arm-smmu 5000000.iommu: Unhandled context fault: fsr=0x402, iova=0xffffffb000, fsynr=0x0, cbfrsynra=0xc01, cb=3 > > Signed-off-by: Laurentiu Tudor <laurentiu.tudor@xxxxxxx> Applied, thanks!
