Enable uart2 and uart3 for imx8qm-mek board.
Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 26 ++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 0b34cc2250e1..6d50838ad17d 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -47,6 +47,18 @@ &lpuart0 {
status = "okay";
};
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "okay";
+};
+
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart3>;
+ status = "okay";
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -118,6 +130,20 @@ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
+ IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <
+ IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020
+ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
