On Tue, Aug 22, 2023 at 02:50:07AM +0200, Marek Vasut wrote: > The PDK2 carrier board had to be manually patched to obtain working PCIe > with the i.MX8MP DHCOM SoM so far, because the PCIe clock generator has > not been connected to the PCIe block REF_PAD_CLK inputs. > > Switch to use of HSIO PLL as the clock source for the PCIe block instead, > and use the REF_PAD_CLK as outputs to generate PCIe clock from the SoC. > This way, it is not necessary to patch the PDK2 in any way to obtain a > working PCIe. > > Note that PDK3 has PCIe clock generator always connected to REF_PAD_CLK > and is not affected. > > Signed-off-by: Marek Vasut <marex@xxxxxxx> Applied, thanks!
