Regards, unicornx Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx> 于2023年9月22日周五 18:40写道： > > Ben Dooks wrote: > > On 20/09/2023 07:40, Chen Wang wrote: > > > From: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx> > > > > > > Add quirk to skip setting the input clock rate for the uarts on the > > > Sophgo SG2042 SoC similar to the StarFive JH7100. > > > > I'd love an actual explanation of why this is necessary here. > > Makes sense. For the JH7100 the commit message is: > > On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to > exactly 16 * 115200Hz and many other common bitrates. Trying this will > only result in a higher input clock, but low enough that the UART's > internal divisor can't come close enough to the baud rate target. > So rather than try to set the input clock it's better to skip the > clk_set_rate call and rely solely on the UART's internal divisor. > > @Chen Wang is this also true for the SG2042? > > /Emil Emil & Ben, I need to double-confirm this with sophgo engineers. Because they are off work now, I will probably get back to you later next week.
