According to TRM for J721S2, SDR104 speed mode is supported by the SoC but its capabilities were masked in device tree. Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card in J721S2 SoC. Also add itap delay select value for DDR50 High Speed Mode. [+] Refer to : section 12.3.6.1.1 MMCSD Features, in J721S2 TRM - https://www.ti.com/lit/zip/spruj28 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Bhavya Kapoor <b-kapoor@xxxxxx> Reviewed-by: Udit Kumar <u-kumar1@xxxxxx> --- Changelog v2->v3: - Add Itap Delay Select value for DDR50 SD High Speed Mode Link to v2 patch : https://lore.kernel.org/all/20230412121415.860447-1-b-kapoor@xxxxxx/ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 084f8f5b6699..a5ab301b14f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -766,11 +766,10 @@ main_sdhci1: mmc@4fb0000 { ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask = <0x00000003 0x00000000>; status = "disabled"; }; -- 2.39.2
