Yo, On Wed, Sep 20, 2023 at 02:40:32PM +0800, Chen Wang wrote: > Milk-V Pioneer motherboard is powered by SOPHON's SG2042. > > SG2042 is server grade chip with high performance, low power > consumption and high data throughput. > Key features: > - 64 RISC-V cpu cores which implements IMAFDC That's not quite true though, is it? > - 4 cores per cluster, 16 clusters on chip > - ...... What's a "....."? ;) > > More info is available at [1]. > > [1]: https://en.sophgo.com/product/introduce/sg2042.html Link: please. > Currently only support booting into console with only uart, > other features will be added soon later. > > Acked-by: Xiaoguang Xing <xiaoguang.xing@xxxxxxxxxx> > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@xxxxxxxxxx> > Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxxxx> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx> > Signed-off-by: Chen Wang <wangchen20@xxxxxxxxxxx> There are 4 sign-offs here. Surely some of these should be co-developed-bys? > + cpu0: cpu@0 { > + compatible = "thead,c920", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; Please also add riscv,isa-base & riscv,isa-extensions. > + reg = <0>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache0>; > + mmu-type = "riscv,sv39"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > new file mode 100644 > index 000000000000..747fd9764c95 > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > @@ -0,0 +1,439 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT You should add () around the GPL-2.0 OR MIT. > +/* > + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. > + */ > + > +/dts-v1/; > +#include <dt-bindings/interrupt-controller/irq.h> > + > +#include "sg2042-cpus.dtsi" > + > +#define SOC_PERIPHERAL_IRQ(nr) (nr) Why? What does this do? Where was it copied from? > + > +/ { > + compatible = "sophgo,sg2042"; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-noncoherent; > + > + aliases { > + serial0 = &uart0; > + }; > + > + /* the mem node will be updated by ZSBL. */ huh? So these are random numbers below? Either put something useful here or delete it please. > + memory@0 { > + device_type = "memory"; > + reg = <0x00000000 0x00000000 0x00000000 0x00000000>; > + }; > + > + memory@1 { > + device_type = "memory"; > + reg = <0x00000000 0x00000001 0x00000000 0x00000000>; > + }; > + > + memory@2 { > + device_type = "memory"; > + reg = <0x00000000 0x00000002 0x00000000 0x00000000>; > + }; > + > + memory@3 { > + device_type = "memory"; > + reg = <0x00000000 0x00000003 0x00000000 0x00000000>; > + }; > + soc: soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clint_mswi: interrupt-controller@7094000000 { > + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; > + reg = <0x00000070 0x94000000 0x00000000 0x00004000>; & nak to this without further explanation! Thanks, Conor.
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