On 13.09.2023 10:38, Geert Uytterhoeven wrote: > Hi Krzysztof, > > On Wed, Sep 13, 2023 at 10:26 AM Krzysztof Kozlowski > <krzysztof.kozlowski@xxxxxxxxxx> wrote: >> On 13/09/2023 10:23, Geert Uytterhoeven wrote: >>>> >>>>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1", >>>>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk", >>>>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk", >>>>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk", >>>>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk", >>>>> + "uniphy2_nss_tx_clk", "xo_board_clk"; >>>> >>>> You are using clock indices. Please drop clock-names. >>> >>> What do you mean by "using clock indices"? >>> Note that the "clock-names" property is required according to the DT bindings. >> >> Indeed, thanks for pointing this out. Probably bindings should be changed. > > But what's so great about not having "clock-names"? > There are _14_ input clocks. clk_parent_data has an "index" member, which lets us bind clocks[n] to parent[n]. With the DT properties being ABI, including the order of entries within, that lets us get rid of clock-names and the matching is marginally faster. Konrad
