Hi Eddie,
On 2014-12-23 08:02, Eddie Huang wrote:
Hi,
On Mon, 2014-12-22 at 09:07 +0000, Marc Zyngier wrote:
On 20/12/14 20:07, Arnd Bergmann wrote:
> On Wednesday 17 December 2014 15:01:29 Marc Zyngier wrote:
>>
>> Indeed, as described in the documentation:
>>
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0471b/CHDIFAEE.html
>>
>> Also it is worth noticing that given how GICV is placed, it will
never
>> work with 64K pages and virtualization. Pretty sad.
>
> Does this mean no VGIC support on this platform so you have to
emulate it
> in order to run virtual machines with 64K pages, or does it mean
that
> it's impossible to use that way because you can't emulate it?
As Peter said, this is not a configuration we're willing to support:
- we don't have a API to tell userspace emulation about interrupts
generated by the generic timers
- we could move the whole GIC emulation into the kernel (at the
moment,
only the distributor is there), but that would be a complete
nightmare
It really looks like a case of "let's drop a bunch of 64bit cores
into
an existing SoC". Shame people can't read integration guidelines...
M.
MT8173 use GIC-400. We check GIC-400 TRM that VGIC address is not
64KB
alignment. but GIC-500 (GICv3) VGIC base address is. We also check
3.19-rc1 arm64 device tree, amd-seattle-soc.dtsi VGIC is 64KB
alignment,
but arm juno.dts is not, they are both GIC-400. So we are a little
confused, and still try to figure out what is the correct address.
I'm afraid you're missing the point.
It is not a matter of alignment, but a matter of having put the GICV
region in the same 64K page as the rest of the GIC. Which means that
if the hypervisor (KVM or Xen) wants to map the GICV region inside the
guest, it will also be forced to give it access to GICC, GICD, and
GICH.
Goodbye isolation, see your hypervisor going down at the first buggy
guest,
not to mention all kind of other nice hacks...
I could understand the need to tightly pack everything on a 32bit
system,
but doing so on a 64bit system without consideration of the page size
is a bit of a bummer.
Neverthless, MT8173 SoC already use 0x10224000 and 0x10225000 as VGIC
base address.
Then its fate is sealed virtualization wise.
Thanks,
M.
--
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