On 07/09/2023 03:01, Adam Ford wrote: > The Ethernet PHY interrupt pin is routed to GPIO_58. Create a > PHY node to configure this GPIO for the interrupt to avoid polling. > > Signed-off-by: Adam Ford <aford173@xxxxxxxxx> > > diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts > index 738189ddc8d5..19869ef906a8 100644 > --- a/arch/arm/boot/dts/ti/omap/am3517-evm.dts > +++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts > @@ -172,11 +172,24 @@ hsusb1_phy: hsusb1_phy { > &davinci_emac { > pinctrl-names = "default"; > pinctrl-0 = <ðernet_pins>; > + phy-mode = "rmii"; > + phy-handle = <ðphy0>; > status = "okay"; > }; > > &davinci_mdio { > + #address-cells = <1>; > + #size-cells = <0>; > status = "okay"; > + > + ethphy0: ethernet-phy@0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&enet_phy_pins>; > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + interrupt-parent = <&gpio2>; > + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; /* gpio_58 */ > + }; > }; > > &dss { > @@ -257,6 +270,12 @@ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ > >; > }; > > + enet_phy_pins: pinmux_ent_phy_pins { Nope. This looks like pasted from some old downstream tree. Please rewrite downstream code to match upstream. Best regards, Krzysztof