On Tue, Aug 22, 2023 at 08:42:18PM +0530, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based upon the PCIe gen speed. > > Adding the Operating Performance Points table allows to adjust power domain > performance state, depending on the PCIe gen speed. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 81971be4..779339c 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -121,6 +121,10 @@ properties: > description: GPIO controlled connection to WAKE# signal > maxItems: 1 > > + operating-points-v2: true > + opp-table: > + type: object > + > required: > - compatible > - reg > -- > 2.7.4 > -- மணிவண்ணன் சதாசிவம்
