On 11/08/2023 20:44, Vignesh Raghavendra wrote: > From: Bryan Brattlof <bb@xxxxxx> > > The AM62Px is an extension of the existing Sitara AM62x low-cost family > of application processors built for Automotive and Linux Application > development. Scalable Arm Cortex-A53 performance and embedded features, > such as: multi high-definition display support, 3D-graphics > acceleration, 4K video acceleration, and extensive peripherals make the > AM62Px well-suited for a broad range of automation and industrial > application, including automotive digital instrumentation, automotive > displays, industrial HMI, and more. > > Some highlights of AM62P SoC are: > * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. > Dual/Single core variants are provided in the same package to allow HW > compatible designs. > * One Device manager Cortext-R5F for system power and resource > management, and one Cortex-R5F for Functional Safety or > general-purpose usage. > * One 3D GPU up to 50 GLFOPS > * H.264/H.265 Video Encode/Decode. > * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or > 2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution > * Integrated Giga-bit Ethernet switch supporting up to a total of two > external ports (TSN capable). > * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for > NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, > 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. > * Dedicated Centralized Hardware Security Module with support for secure > boot, debug security and crypto acceleration and trusted execution > environment. > * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. > * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, > enabling battery powered system design. > > For those interested, more details about this SoC can be found in the > Technical Reference Manual here: > > https://www.ti.com/lit/pdf/spruj83 > > Signed-off-by: Bryan Brattlof <bb@xxxxxx> > Acked-by: Andrew Davis <afd@xxxxxx> > Reviewed-by: Dhruva Gole <d-gole@xxxxxx> > Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx> > --- > arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 136 ++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi | 15 +++ > arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 32 +++++ > arch/arm64/boot/dts/ti/k3-am62p.dtsi | 122 ++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 107 +++++++++++++++ > arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 + > 6 files changed, 415 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi > new file mode 100644 > index 000000000000..c24ff905437f > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi > @@ -0,0 +1,136 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree file for the AM62P main domain peripherals > + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +&cbass_main { > + oc_sram: sram@70000000 { > + compatible = "mmio-sram"; > + reg = <0x00 0x70000000 0x00 0x10000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00 0x00 0x70000000 0x10000>; > + }; > + > + gic500: interrupt-controller@1800000 { > + compatible = "arm,gic-v3"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ > + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ > + <0x01 0x00000000 0x00 0x2000>, /* GICC */ > + <0x01 0x00010000 0x00 0x1000>, /* GICH */ > + <0x01 0x00020000 0x00 0x2000>; /* GICV */ > + /* > + * vcpumntirq: > + * virtual CPU interface maintenance interrupt > + */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic_its: msi-controller@1820000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x00 0x01820000 0x00 0x10000>; > + socionext,synquacer-pre-its = <0x1000000 0x400000>; > + msi-controller; > + #msi-cells = <1>; > + }; > + }; > + > + dmss: bus@48000000 { > + bootph-all; > + compatible = "simple-mfd"; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-ranges; > + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; > + > + ti,sci-dev-id = <25>; My v1 concerns are still valid. > + > + secure_proxy_main: mailbox@4d000000 { > + bootph-all; > + compatible = "ti,am654-secure-proxy"; > + #mbox-cells = <1>; > + reg-names = "target_data", "rt", "scfg"; > + reg = <0x00 0x4d000000 0x00 0x80000>, > + <0x00 0x4a600000 0x00 0x80000>, > + <0x00 0x4a400000 0x00 0x80000>; > + interrupt-names = "rx_012"; > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; Best regards, Krzysztof
