在 2023/8/8 下午8:05, Conor Dooley 写道:
Hey,
On Mon, Aug 07, 2023 at 03:40:42PM +0800, Yinbo Zhu wrote:
Loongson GPIO controllers come in multiple variants that are compatible
except for certain register offset values. Add support in yaml file for
device properties allowing to specify them in DT.
Signed-off-by: Yinbo Zhu <zhuyinbo@xxxxxxxxxxx>
---
.../bindings/gpio/loongson,ls-gpio.yaml | 40 ++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
index fb86e8ce6349..fc51cf40fccd 100644
--- a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
@@ -14,6 +14,7 @@ properties:
enum:
- loongson,ls2k-gpio
- loongson,ls7a-gpio
+ - loongson,ls2k1000-gpio
If you're adding new compatibles that depend on the new offset
properties to function, they could be set up with the existing
"ls2k-gpio" as a fallback, so that further driver changes are not
required when you add ones for the 2k500 etc.
okay, I got it.
reg:
maxItems: 1
@@ -29,6 +30,33 @@ properties:
gpio-ranges: true
+ loongson,gpio-conf-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ This option indicate this GPIO configuration register offset address.
+
+ loongson,gpio-out-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ This option indicate this GPIO output register offset address.
+
+ loongson,gpio-in-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ This option indicate this GPIO input register offset address.
+
+ loongson,gpio-ctrl-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ This option indicate this GPIO control mode, where '0' represents
+ bit control mode and '1' represents byte control mode.
How is one supposed to know which of these modes to use?
Byte mode is to access by byte, such as gpio3, the base address of the
gpio controller is offset by 3 bytes as the access address of gpio3.
The bit mode is the normal mode that like other platform gpio and it is
to access by bit.
If both modes are supported, it is recommended to prioritize using byte
mode that according to spec.
+ loongson,gpio-inten-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ This option indicate this GPIO interrupt enable register offset
+ address.
+
tbh, I want to leave the final say on this stuff to Krzysztof or Rob.
I'm not really sure what the best way to do to support your GPIO
controllers is & I don't understand your hardware sufficiently to come
up with an approach that I would use had I been in your shoes.
okay, I got it.
Thanks,
Yinbo
interrupts:
minItems: 1
maxItems: 64
@@ -39,6 +67,11 @@ required:
- ngpios
- "#gpio-cells"
- gpio-controller
+ - loongson,gpio-conf-offset
+ - loongson,gpio-in-offset
+ - loongson,gpio-out-offset
+ - loongson,gpio-ctrl-mode
+ - loongson,gpio-inten-offset
- gpio-ranges
- interrupts
@@ -49,11 +82,16 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
gpio0: gpio@1fe00500 {
- compatible = "loongson,ls2k-gpio";
+ compatible = "loongson,ls2k1000-gpio";
reg = <0x1fe00500 0x38>;
ngpios = <64>;
#gpio-cells = <2>;
gpio-controller;
+ loongson,gpio-conf-offset = <0>;
+ loongson,gpio-in-offset = <0x20>;
+ loongson,gpio-out-offset = <0x10>;
+ loongson,gpio-ctrl-mode = <0>;
+ loongson,gpio-inten-offset = <0x30>;
gpio-ranges = <&pctrl 0 0 15>,
<&pctrl 16 16 15>,
<&pctrl 32 32 10>,
--
2.20.1
