On 08/08/2023 21:48, Alexander Stein wrote:
> Convert Amlogic AXG Audio Clock Controller binding to yaml.
>
> Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxx>
> ---
> As it is the same directory I picked the same maintainers as
> Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml.
>
> I'm not 100% sure about the optional clocks constraints. As mentioned in
> the .txt version only pclk is mandatory, others are optional.
>
> .../bindings/clock/amlogic,axg-audio-clkc.txt | 59 --------
> .../clock/amlogic,axg-audio-clkc.yaml | 136 ++++++++++++++++++
> 2 files changed, 136 insertions(+), 59 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
> deleted file mode 100644
> index 3a8948c04bc9..000000000000
> --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
> +++ /dev/null
> @@ -1,59 +0,0 @@
> -* Amlogic AXG Audio Clock Controllers
> -
> -The Amlogic AXG audio clock controller generates and supplies clock to the
> -other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
> -devices.
> -
> -Required Properties:
> -
> -- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
> - "amlogic,g12a-audio-clkc" for G12A,
> - "amlogic,sm1-audio-clkc" for S905X3.
> -- reg : physical base address of the clock controller and length of
> - memory mapped region.
> -- clocks : a list of phandle + clock-specifier pairs for the clocks listed
> - in clock-names.
> -- clock-names : must contain the following:
> - * "pclk" - Main peripheral bus clock
> - may contain the following:
> - * "mst_in[0-7]" - 8 input plls to generate clock signals
> - * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
> - components.
> - * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
> - components.
> -- resets : phandle of the internal reset line
> -- #clock-cells : should be 1.
> -- #reset-cells : should be 1 on the g12a (and following) soc family
> -
> -Each clock is assigned an identifier and client nodes can use this identifier
> -to specify the clock which they consume. All available clocks are defined as
> -preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
> -used in device tree sources.
> -
> -Example:
> -
> -clkc_audio: clock-controller@0 {
> - compatible = "amlogic,axg-audio-clkc";
> - reg = <0x0 0x0 0x0 0xb4>;
> - #clock-cells = <1>;
> -
> - clocks = <&clkc CLKID_AUDIO>,
> - <&clkc CLKID_MPLL0>,
> - <&clkc CLKID_MPLL1>,
> - <&clkc CLKID_MPLL2>,
> - <&clkc CLKID_MPLL3>,
> - <&clkc CLKID_HIFI_PLL>,
> - <&clkc CLKID_FCLK_DIV3>,
> - <&clkc CLKID_FCLK_DIV4>,
> - <&clkc CLKID_GP0_PLL>;
> - clock-names = "pclk",
> - "mst_in0",
> - "mst_in1",
> - "mst_in2",
> - "mst_in3",
> - "mst_in4",
> - "mst_in5",
> - "mst_in6",
> - "mst_in7";
> - resets = <&reset RESET_AUDIO>;
> -};
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
> new file mode 100644
> index 000000000000..629fa3a81cf7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
> @@ -0,0 +1,136 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic AXG Audio Clock Controller
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> + - Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> + - Jian Hu <jian.hu@xxxxxxxxxxx>
> + - Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx>
> +
> +description:
> + The Amlogic AXG audio clock controller generates and supplies clock to the
> + other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
> + devices.
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,axg-audio-clkc
> + - amlogic,g12a-audio-clkc
> + - amlogic,sm1-audio-clkc
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
reg is usually the second property.
> +
> + clocks:
> + minItems: 1
> + maxItems: 11
> +
> + clock-names:
> + oneOf:
> + - const: pclk
> + - items:
> + - const: pclk
> + - const: mst_in0
> + - const: mst_in1
> + - const: mst_in2
> + - const: mst_in3
> + - const: mst_in4
> + - const: mst_in5
> + - const: mst_in6
> + - const: mst_in7
> + - items:
> + - const: pclk
> + - const: slv_sclk0
> + - const: slv_sclk1
> + - const: slv_sclk2
> + - const: slv_sclk3
> + - const: slv_sclk4
> + - const: slv_sclk5
> + - const: slv_sclk6
> + - const: slv_sclk7
> + - const: slv_sclk8
> + - const: slv_sclk9
> + - items:
> + - const: pclk
> + - const: slv_lrclk0
> + - const: slv_lrclk1
> + - const: slv_lrclk2
> + - const: slv_lrclk3
> + - const: slv_lrclk4
> + - const: slv_lrclk5
> + - const: slv_lrclk6
> + - const: slv_lrclk7
> + - const: slv_lrclk8
> + - const: slv_lrclk9
> +
> + resets:
> + description: internal reset line
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - reg
> + - clocks
> + - clock-names
> + - resets
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - amlogic,g12a-audio-clkc
> + - amlogic,sm1-audio-clkc
> + then:
> + required:
> + - '#reset-cells'
else:
properties:
'#reset-cells': false
???
You need to constrain the clocks per variant. Probably names are also
specific to each one, so the list of names can be moved here and you
keep just min/maxItems in the top level property.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/axg-clkc.h>
> + #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
> + apb {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clkc_audio: clock-controller@0 {
> + compatible = "amlogic,axg-audio-clkc";
Broken indentation.
> + reg = <0x0 0x0 0x0 0xb4>;
> + #clock-cells = <1>;
> +
> + clocks = <&clkc CLKID_AUDIO>,
> + <&clkc CLKID_MPLL0>,
> + <&clkc CLKID_MPLL1>,
> + <&clkc CLKID_MPLL2>,
> + <&clkc CLKID_MPLL3>,
> + <&clkc CLKID_HIFI_PLL>,
> + <&clkc CLKID_FCLK_DIV3>,
> + <&clkc CLKID_FCLK_DIV4>,
> + <&clkc CLKID_GP0_PLL>;
> + clock-names = "pclk",
> + "mst_in0",
> + "mst_in1",
> + "mst_in2",
> + "mst_in3",
> + "mst_in4",
> + "mst_in5",
> + "mst_in6",
> + "mst_in7";
> + resets = <&reset RESET_AUDIO>;
> + };
And indentation here is even less matching.
> + };
Best regards,
Krzysztof
