On Tue, Aug 08, 2023 at 08:39:39PM +0000, Hawkins, Nick wrote:
> Hi Andrew,
>
> Thank you for your feedback, I have several follow up questions:
>
> > So what you call a PHY is probably a PCS. Please look at the API used
> > in driver/net/pcs/. The real PHYs are external.
>
> I doubled checked the internal PHY is considered a PHY, but I believe
> I can represent it as a PCS.
Is there proper documentation somewhere? register set? Is there
registers to kick off Base1000X/SGMII auto-neg? Somewhere to get the
results of the auto-neg? Since this is Base1000X/SGMII you want to
know if the link between it and the external PHY has established. And
if there is not an external PHY, but an SFP, this auto neg is with the
link peer, not the PHY. If it follows 802.3 clause 37, there should
already be a lot of helper code for you. Is this is licensed core?
> To confirm: I believe you are suggesting that
> we create a driver here for the handling of the internal PHY but not the
> external PHY?
The patches seem to suggest your board has an external Marvell PHY. So
i would expect it to use drivers/net/phy/marvell.c. Other boards,
using other PHYs, would use other PHY drivers.
> If so would it be leveraging the MDIO driver already created in this
> patchset? Or perhaps would it be replacing it for the internal PHY?
Many of the PCS drivers in driver/net/pcs are MDIO devices, so yes, it
would be layered on top of it.
Andrew
