On Tue, Aug 08, 2023 at 09:44:16AM -0500, Andrew Halaney wrote: > On Tue, Aug 08, 2023 at 04:30:05PM +0200, Bartosz Golaszewski wrote: > > On Tue, Aug 8, 2023 at 4:25 PM Andrew Lunn <andrew@xxxxxxx> wrote: > > > > > > > > On Tue, Aug 08, 2023 at 10:13:09AM +0200, Bartosz Golaszewski wrote: > > > > > > Ok so upon some further investigation, the actual culprit is in stmmac > > > > > > platform code - it always tries to register an MDIO bus - independent > > > > > > of whether there is an actual mdio child node - unless the MAC is > > > > > > marked explicitly as having a fixed-link. > > > > > > > > > > > > When I fixed that, MAC1's probe is correctly deferred until MAC0 has > > > > > > created the MDIO bus. > > > > > > > > > > > > Even so, isn't it useful to actually reference the shared MDIO bus in some way? > > > > > > > > > > > > If the schematics look something like this: > > > > > > > > > > > > -------- ------- > > > > > > | MAC0 |--MDIO-----| PHY | > > > > > > -------- | | ------- > > > > > > | | > > > > > > -------- | | ------- > > > > > > | MAC1 |-- ----| PHY | > > > > > > -------- ------- > > > > > > > > > > > > Then it would make sense to model it on the device tree? > > > > > > > > > > So I think what you're saying is that MAC0 and MAC1's have MDIO bus > > > > > masters, and the hardware designer decided to tie both together to > > > > > a single set of clock and data lines, which then go to two PHYs. > > > > > > > > The schematics I have are not very clear on that, but now that you > > > > mention this, it's most likely the case. > > > > > > I hope not. That would be very broken. As Russell pointed out, MDIO is > > > not multi-master. You need to check with the hardware designer if the > > > schematics are not clear. > > > > Sorry, it was not very clear. It's the case that two MDIO masters > > share the MDC and data lines. > > I'll make the water muddier (hopefully clearer?). I have access to the > board schematic (not SIP/SOM stuff though), but that should help here. > > MAC0 owns its own MDIO bus (we'll call it MDIO0). It is pinmuxed to > gpio8/gpio9 for mdc/mdio. MAC1 owns its own bus (MDIO1) which is > pinmuxed to gpio21/22. > > On MDIO0 there are two SGMII ethernet phys. One is connected to MAC0, > one is connected to MAC1. > > MDIO1 is not connected to anything on the board. So there is only one > MDIO master, MAC0 on MDIO0, and it manages the ethernet phy for both > MAC0/MAC1. > > Does that make sense? I don't think from a hardware design standpoint > this is violating anything, it isn't a multimaster setup on MDIO. That all sounds sane, thanks. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
