Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These effectively need two parent clocks. Use GATE_LINK to handle this. Reported-by: kernel test robot <lkp@xxxxxxxxx> Closes:https://lore.kernel.org/oe-kbuild-all/202308040120.7KQxScIs-lkp@xxxxxxxxx/ Signed-off-by: Elaine Zhang <zhangqing@xxxxxxxxxxxxxx> --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-gate-link.c | 120 +++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 7 ++ drivers/clk/rockchip/clk.h | 22 +++++ 4 files changed, 150 insertions(+) create mode 100644 drivers/clk/rockchip/clk-gate-link.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 36894f6a7022..87cc39d54f72 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o clk-rockchip-y += clk-mmc-phase.o clk-rockchip-y += clk-muxgrf.o clk-rockchip-y += clk-ddr.o +clk-rockchip-y += clk-gate-link.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_CLK_PX30) += clk-px30.o diff --git a/drivers/clk/rockchip/clk-gate-link.c b/drivers/clk/rockchip/clk-gate-link.c new file mode 100644 index 000000000000..d4bbef4a067b --- /dev/null +++ b/drivers/clk/rockchip/clk-gate-link.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Fuzhou Rockchip Electronics Co., Ltd + */ +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/string.h> +#include "clk.h" + +/** + * struct clk_gate_link - gating link clock + * + * @gate: handle clk gate + * @link: links clk + */ +struct clk_gate_link { + struct clk_gate gate; + struct clk *link; +}; + +#define to_clk_gate_link(_gate) container_of(_gate, struct clk_gate_link, gate) + +static int clk_gate_link_enable(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_gate_endisable(hw, 1); + clk_enable(gate->link); + + return 0; +} + +static void clk_gate_link_disable(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_gate_endisable(hw, 0); + clk_disable(gate->link); +} + +static int clk_gate_link_is_enabled(struct clk_hw *hw) +{ + return clk_gate_is_enabled(hw); +} + +static int clk_gate_link_prepare(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + return clk_prepare(gate->link); +} + +static void clk_gate_link_unprepare(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_unprepare(gate->link); +} + +const struct clk_ops clk_gate_link_ops = { + .prepare = clk_gate_link_prepare, + .unprepare = clk_gate_link_unprepare, + .enable = clk_gate_link_enable, + .disable = clk_gate_link_disable, + .is_enabled = clk_gate_link_is_enabled, +}; + +struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, + const char *name, const char *parent_name, + unsigned int link_id, u8 flags, + void __iomem *gate_offset, u8 gate_shift, + u8 gate_flags, spinlock_t *lock) +{ + struct clk_gate_link *gate_link; + struct clk_init_data init = {}; + struct clk **clks; + struct clk *clk_link; + + if (gate_flags & CLK_GATE_HIWORD_MASK) { + if (gate_shift > 15) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-ENOMEM); + } + } + + /* allocate the gate */ + gate_link = kzalloc(sizeof(*gate_link), GFP_KERNEL); + if (!gate_link) + return ERR_PTR(-ENOMEM); + + clks = ctx->clk_data.clks; + gate_link->link = clks[link_id]; + + init.name = name; + init.ops = &clk_gate_link_ops; + init.flags = flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = 1; + + /* struct clk_gate assignments */ + gate_link->gate.reg = gate_offset; + gate_link->gate.bit_idx = gate_shift; + gate_link->gate.flags = gate_flags; + gate_link->gate.lock = lock; + gate_link->gate.hw.init = &init; + + clk_link = clk_register(NULL, &gate_link->gate.hw); + if (IS_ERR(clk_link)) { + kfree(gate_link); + pr_err("%s clk_register field\n", name); + return ERR_CAST(clk_link); + } + + return clk_link; +} +EXPORT_SYMBOL_GPL(rockchip_clk_register_gate_link); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 4059d9365ae6..d981ef6c5487 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -509,6 +509,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ctx->reg_base + list->gate_offset, list->gate_shift, list->gate_flags, &ctx->lock); break; + + case branch_gate_link: + clk = rockchip_clk_register_gate_link(ctx, list->name, + list->parent_names[0], list->link_id, flags, + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); + break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 758ebaf2236b..b49e3cede33a 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -517,6 +517,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_gate_link, branch_mmc, branch_inverter, branch_factor, @@ -529,6 +530,7 @@ struct rockchip_clk_branch { enum rockchip_clk_branch_type branch_type; const char *name; const char *const *parent_names; + unsigned int link_id; u8 num_parents; unsigned long flags; int muxdiv_offset; @@ -842,6 +844,20 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define GATE_LINK(_id, cname, pname, _linkid, f, o, b, gf) \ + { \ + .id = _id, \ + .branch_type = branch_gate_link, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .link_id = _linkid, \ + .flags = f, \ + .gate_offset = o, \ + .gate_shift = b, \ + .gate_flags = gf, \ + } + #define MMC(_id, cname, pname, offset, shift) \ { \ .id = _id, \ @@ -1002,6 +1018,12 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, unsigned long flags, spinlock_t *lock); +struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, + const char *name, const char *parent_name, + unsigned int link_id, u8 flags, + void __iomem *gate_offset, u8 gate_shift, + u8 gate_flags, spinlock_t *lock); + #ifdef CONFIG_RESET_CONTROLLER void rockchip_register_softrst_lut(struct device_node *np, const int *lookup_table, -- 2.17.1
