On Fri, Aug 04, 2023 at 01:20:34PM -0700, Jakub Kicinski wrote:
> CC: Conor
>
> in case the missing CC is the reason for higher than usual
> review latency :)
You even CCed the +dt address so the mail ended up in the right place!
I doubt not having me on CC is the reason for the delay, seems to be a
pattern that the conversion patches end up being Rob's to look at. I at
least find them more difficult to review than new bindings.
It looks like Rob's comments on v(N-1) were resolved, but something here
looks odd to me.
> > + clocks:
> > + minItems: 1
> > + items:
> > + - description: MAC IP clock
> > + - description: RMII RCLK gate for AST2500/2600
> > +
> > + clock-names:
> > + minItems: 1
> > + maxItems: 2
> > + contains:
> > + enum:
> > + - MACCLK
> > + - RCLK
I don't really understand the pattern being used here.
> > -- clocks: In accordance with the generic clock bindings. Must describe the MAC
> > - IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
> > - required MAC clock must be the first cell.
The order in the original binding was strict & the MAC clock had to come
first. What's in the new yaml one is more permissive & I think it should
be
clock-names:
minItems: 1
items:
- const: MACCLK
- const: RCLK
unless of course I am missing something that is...
> > -- clock-names:
> > -
> > - - "MACCLK": The MAC IP clock
> > - - "RCLK": Clock gate for the RMII RCLK
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