On Wed, Aug 02, 2023 at 10:58:42AM +0800, niravkumar.l.rabara@xxxxxxxxx wrote: > From: Niravkumar L Rabara <niravkumar.l.rabara@xxxxxxxxx> > > Add clock ID definitions for Intel Agilex5 SoCFPGA. > The registers in Agilex5 handling the clock is named as clock manager. > > Signed-off-by: Teh Wen Ping <wen.ping.teh@xxxxxxxxx> > Reviewed-by: Dinh Nguyen <dinguyen@xxxxxxxxxx> > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@xxxxxxxxx> Damn, I was too late - you already sent a v3 :/ However, there only seems to be a v3 of this one patch and it was sent in reply to the v2 series? The normal thing to do is resend the entire series, not just one patch, as a new thread. Not using a new thread may make it harder to apply & will also bury the email in people's mailboxes that use things like mutt. A single patch as a reply is also confusing, as the rest of the v3 looks like it is missing! Thanks, Conor.
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