Add the new option 'mxl,control-gate'. Gate clocks can be controlled
either from this cgu clk driver or directly from power management
driver/daemon. It is dependent on the power policy/profile requirements
of the end product. To take control of gate clks from this driver, add the
name of the gate to this <mxl,control-gate> devicetree property.
Please refer to 'drivers/clk/x86/clk-lgm.c' source file for the gate names.
Signed-off-by: Florian Eckert <fe@xxxxxxxxxx>
---
.../devicetree/bindings/clock/intel,cgu-lgm.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
index 76609a390429..755d13a65477 100644
--- a/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
+++ b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
@@ -28,6 +28,16 @@ properties:
'#clock-cells':
const: 1
+ mxl,control-gate:
+ description:
+ Gate clocks can be controlled either from this cgu clk driver or
+ directly from power management driver/daemon. It is dependent on the
+ power policy/profile requirements of the end product. To take
+ control of gate clks from this driver, add the name of the gate
+ to this <mxl,control-gate> devicetree property. Please refer to
+ drivers/clk/x86/clk-lgm.c source file for the gate names.
+ $ref: /schemas/types.yaml#/definitions/string-array
+
required:
- compatible
- reg
@@ -41,6 +51,7 @@ examples:
compatible = "intel,cgu-lgm";
reg = <0xe0200000 0x33c>;
#clock-cells = <1>;
+ mxl,control-gate = "g_gptc0", "g_gptc1";
};
...
--
2.30.2
