Gate clocks can be controlled either from this cgu clk driver or directly from power management driver/daemon. It is dependent on the power policy/profile requirements of the end product. To take control of gate clks from this driver. Until now, the source code had to be changed for this purpose by adding the flag 'GATE_CLK_HW' to the LGM_GATE macro in the source file 'drivers/clk/x86/clk-lgm.c'. This can be better handled via the device tree, so that the source no longer needs to be changed. For this purpose, a new option 'mxl,control-gate' is added, which specifies that the gate is controlled by this driver. Florian Eckert (2): clk: mxl: add mxl,control-gate dts property dt-bindings: clock: intel,cgu-lgm: add mxl,control-gate option .../bindings/clock/intel,cgu-lgm.yaml | 11 +++++++ drivers/clk/x86/clk-cgu.c | 30 +++++++++++-------- 2 files changed, 28 insertions(+), 13 deletions(-) -- 2.30.2
