There are only one set of CAN pins available on these chips.
Specify these as the default to avoid redundancy in board device trees.
Signed-off-by: John Watts <contact@xxxxxxxxxx>
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 4086c0cc0f9d..b27c3fc13b0d 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -898,6 +898,8 @@ can0: can@2504000 {
interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CAN0>;
resets = <&ccu RST_BUS_CAN0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins>;
status = "disabled";
};
@@ -907,6 +909,8 @@ can1: can@2504400 {
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CAN1>;
resets = <&ccu RST_BUS_CAN1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins>;
status = "disabled";
};
};
--
2.41.0
