Add initial devicetree for Loongson-1 boards, including
LSGZ_1B_DEV and SMARTLOONG_1C board.
These basic DTs contain CPU, clock and core INTC.
Signed-off-by: Keguang Zhang <keguang.zhang@xxxxxxxxx>
---
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 3 +
arch/mips/boot/dts/loongson/loongson1.dtsi | 22 ++++++
arch/mips/boot/dts/loongson/loongson1b.dtsi | 75 +++++++++++++++++++
arch/mips/boot/dts/loongson/loongson1c.dtsi | 29 +++++++
arch/mips/boot/dts/loongson/lsgz_1b_dev.dts | 25 +++++++
arch/mips/boot/dts/loongson/smartloong_1c.dts | 25 +++++++
7 files changed, 180 insertions(+)
create mode 100644 arch/mips/boot/dts/loongson/loongson1.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson1b.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson1c.dtsi
create mode 100644 arch/mips/boot/dts/loongson/lsgz_1b_dev.dts
create mode 100644 arch/mips/boot/dts/loongson/smartloong_1c.dts
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 928f38a79dff..2e040b1ba97b 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -6,6 +6,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
subdir-$(CONFIG_MACH_INGENIC) += ingenic
subdir-$(CONFIG_LANTIQ) += lantiq
subdir-$(CONFIG_MACH_LOONGSON64) += loongson
+subdir-$(CONFIG_MACH_LOONGSON32) += loongson
subdir-$(CONFIG_SOC_VCOREIII) += mscc
subdir-$(CONFIG_MIPS_MALTA) += mti
subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
index 5c6433e441ee..9d95f1351d5f 100644
--- a/arch/mips/boot/dts/loongson/Makefile
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -6,4 +6,7 @@ dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
+dtb-$(CONFIG_LOONGSON1B_LSGZ_DEV) += lsgz_1b_dev.dtb
+dtb-$(CONFIG_LOONGSON1C_SMARTLOONG) += smartloong_1c.dtb
+
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson1.dtsi b/arch/mips/boot/dts/loongson/loongson1.dtsi
new file mode 100644
index 000000000000..a2b5c828bbbd
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson1.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Keguang Zhang <keguang.zhang@xxxxxxxxx>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/loongson,ls1x-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_intc: interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+ #address-cells = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson1b.dtsi b/arch/mips/boot/dts/loongson/loongson1b.dtsi
new file mode 100644
index 000000000000..784ae9b6572d
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson1b.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Keguang Zhang <keguang.zhang@xxxxxxxxx>
+ */
+
+/dts-v1/;
+#include "loongson1.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ #clock-cells = <1>;
+ clocks = <&clkc LS1X_CLKID_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-44000000 {
+ opp-hz = /bits/ 64 <44000000>;
+ };
+ opp-47142000 {
+ opp-hz = /bits/ 64 <47142000>;
+ };
+ opp-50769000 {
+ opp-hz = /bits/ 64 <50769000>;
+ };
+ opp-55000000 {
+ opp-hz = /bits/ 64 <55000000>;
+ };
+ opp-60000000 {
+ opp-hz = /bits/ 64 <60000000>;
+ };
+ opp-66000000 {
+ opp-hz = /bits/ 64 <66000000>;
+ };
+ opp-73333000 {
+ opp-hz = /bits/ 64 <73333000>;
+ };
+ opp-82500000 {
+ opp-hz = /bits/ 64 <82500000>;
+ };
+ opp-94285000 {
+ opp-hz = /bits/ 64 <94285000>;
+ };
+ opp-110000000 {
+ opp-hz = /bits/ 64 <110000000>;
+ };
+ opp-132000000 {
+ opp-hz = /bits/ 64 <132000000>;
+ };
+ opp-165000000 {
+ opp-hz = /bits/ 64 <165000000>;
+ };
+ opp-220000000 {
+ opp-hz = /bits/ 64 <220000000>;
+ };
+ };
+
+ clkc: clock-controller@1fe78030 {
+ compatible = "loongson,ls1b-clk";
+ reg = <0x1fe78030 0x8>;
+
+ clocks = <&xtal>;
+ #clock-cells = <1>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson1c.dtsi b/arch/mips/boot/dts/loongson/loongson1c.dtsi
new file mode 100644
index 000000000000..d552e1668984
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson1c.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Keguang Zhang <keguang.zhang@xxxxxxxxx>
+ */
+
+/dts-v1/;
+#include "loongson1.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ #clock-cells = <1>;
+ clocks = <&clkc LS1X_CLKID_CPU>;
+ };
+ };
+
+ clkc: clock-controller@1fe78030 {
+ compatible = "loongson,ls1c-clk";
+ reg = <0x1fe78030 0x8>;
+
+ clocks = <&xtal>;
+ #clock-cells = <1>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/lsgz_1b_dev.dts b/arch/mips/boot/dts/loongson/lsgz_1b_dev.dts
new file mode 100644
index 000000000000..d12c723b0a2b
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/lsgz_1b_dev.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Keguang Zhang <keguang.zhang@xxxxxxxxx>
+ */
+
+/dts-v1/;
+
+#include "loongson1b.dtsi"
+
+/ {
+ compatible = "loongson,lsgz-1b-dev", "loongson,ls1b";
+ model = "LSGZ_1B_DEV Board";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x4000000>;
+ };
+
+ xtal: xtal {
+ compatible = "fixed-clock";
+ clock-frequency = <33000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/smartloong_1c.dts b/arch/mips/boot/dts/loongson/smartloong_1c.dts
new file mode 100644
index 000000000000..64e869acfd86
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/smartloong_1c.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Keguang Zhang <keguang.zhang@xxxxxxxxx>
+ */
+
+/dts-v1/;
+
+#include "loongson1c.dtsi"
+
+/ {
+ compatible = "loongmasses,smartloong-1c", "loongson,ls1c";
+ model = "Smartloong_1C Board";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x2000000>;
+ };
+
+ xtal: xtal {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+};
--
2.39.2
