On Fri, Jul 28, 2023 at 12:29:44AM +0800, Xi Ruoyao wrote: > On Fri, 2023-07-28 at 00:11 +0800, Jisheng Zhang wrote: > > On Thu, Jul 27, 2023 at 08:54:59AM +0800, Xi Ruoyao wrote: > > > On Thu, 2023-07-27 at 08:14 +0800, Xi Ruoyao wrote: > > > > On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote: > > > > > which dts r u using? see below. > > > > > > > > > > > > > > > > > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no > > > > > > patches) can > > > > > > miscompile the kernel? > > > > > > > > /* snip */ > > > > > > > > > > Boot HART ID : 0 > > > > > > Boot HART Domain : root > > > > > > Boot HART Priv Version : v1.11 > > > > > > Boot HART Base ISA : rv64imafdcvx > > > > > > > > > > what? I don't think the mainline dts provide v and x. > > > > > > > > I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi- > > > > 4a.dtb > > > > into /boot and loaded it with u-boot "load" command onto > > > > 0x46000000, and > > > > passed this address to the booti command. > > > > > > > > But maybe I've copied the wrong file or made some other mistake... > > > > I'll > > > > recheck. > > > > > > Hmm, and if I read OpenSBI code correctly, this line reflects the > > > content of the misa CSR, not the DT riscv,isa value. > > > > > > > Aha indeed the "vx" isa extensions are not from the DT riscv,isa > > property. I will try your opensbi/linux/uboot combinations on my > > lpi4a board tomorrow. > > My kernel config attached. Maybe you can find some stupid mistake in > it, I'm not familiar with RISC-V, nor DT-based systems :(. It seems like your kernel config is the problem. I used it and I saw the same result of a panic in riscv_intc_irq: https://gist.github.com/pdp7/1a26ebe20017a3b90c4e9c005f8178e1 This is the config I have been using successfully: https://gist.github.com/pdp7/ecb34ba1e93fc6cfc4dce66d71e14f82 Could you try that config? Linux 6.5-rc3 boots okay when built with it: https://gist.github.com/pdp7/580b072f9a5bf9be87cf88b5f81e50e3 Thanks, Drew
