Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support

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Hi Jisheng,

On Sun, 2023-06-18 at 00:15 +0800, Jisheng Zhang wrote:
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> tree files for the core module and the development board.
> 
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.

Thanks for the excellent work, but when I tried to boot Linux 6.5.0-rc3
on my Lichee Pi 4A it fails with:

## Flattened Device Tree blob at 01f00000
   Booting using the fdt blob at 0x1f00000
   Using Device Tree in place at 0000000001f00000, end 0000000001f050c4

Starting kernel ...

[    0.000000] Linux version 6.5.0-rc3 (lfs@stargazer) (riscv64-lfs-linux-gnu-gcc (GCC) 13.1.0, GNU ld (GNU Binutils) 2.40) #1 SMP PREEMPT Tue Jul 25 13:38:20 CST 2023
[    0.000000] Machine model: Sipeed Lichee Pi 4A
[    0.000000] SBI specification v0.3 detected
[    0.000000] SBI implementation ID=0x1 Version=0x9
[    0.000000] SBI TIME extension detected
[    0.000000] SBI IPI extension detected
[    0.000000] SBI RFENCE extension detected
[    0.000000] earlycon: uart0 at MMIO32 0x000000ffe7014000 (options '115200n8')
[    0.000000] printk: bootconsole [uart0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] OF: reserved mem: 0x0000000000000000..0x000000000003ffff (256 KiB) nomap non-reusable mmode_resv0@0
[    0.000000] Zone ranges:
[    0.000000]   DMA32    [mem 0x0000000000000000-0x00000000ffffffff]
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000001ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000000003ffff]
[    0.000000]   node   0: [mem 0x0000000000040000-0x00000001ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000001ffffffff]
[    0.000000] SBI HSM extension detected
[    0.000000] riscv: base ISA extensions acdfim
[    0.000000] riscv: ELF capabilities acdfim
[    0.000000] percpu: Embedded 17 pages/cpu s38184 r0 d31448 u69632
[    0.000000] Kernel command line: console=ttyS0,115200 earlycon loglevel=7
[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2064384
[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 4.
[    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[    0.000000] Memory: 8145304K/8388608K available (4922K kernel code, 4786K rwdata, 2048K rodata, 2148K init, 393K bss, 243304K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] riscv-intc: 64 local interrupts mapped
[    0.000000] Oops - load access fault [#1]
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.5.0-rc3 #1
[    0.000000] Hardware name: Sipeed Lichee Pi 4A (DT)
[    0.000000] epc : __plic_toggle+0x5a/0x62
[    0.000000]  ra : __plic_init.isra.0+0x2d0/0x462
[    0.000000] epc : ffffffff802ce8ec ra : ffffffff80618816 sp : ffffffff80e03c90
[    0.000000]  gp : ffffffff80ec5bb8 tp : ffffffff80e10d40 t0 : ffffffd900045940
[    0.000000]  t1 : 0000000000000002 t2 : ffffffd90004a10c s0 : ffffffd9fef6ed68
[    0.000000]  s1 : ffffffd900045680 a0 : ffffffc801002080 a1 : 0000000000000002
[    0.000000]  a2 : 0000000000000000 a3 : 00000000000000f4 a4 : 0000000000000001
[    0.000000]  a5 : 0000000000000000 a6 : 0000000000000b40 a7 : ffffffd900045940
[    0.000000]  s2 : ffffffd9fef6ed78 s3 : ffffffff80ef9630 s4 : 0000000000000001
[    0.000000]  s5 : ffffffd9ffff5af8 s6 : 0000000000000001 s7 : ffffffff80815d68
[    0.000000]  s8 : 0000000000000008 s9 : 0000000000000000 s10: ffffffff80815d68
[    0.000000]  s11: ffffffff80b1b1b8 t3 : ffffffff80c003d0 t4 : 0000000000000001
[    0.000000]  t5 : 0000000000000003 t6 : 0000000000000001
[    0.000000] status: 8000000201800100 badaddr: 000000ffd8002080 cause: 0000000000000005
[    0.000000] [<ffffffff802ce8ec>] __plic_toggle+0x5a/0x62
[    0.000000] [<ffffffff8061ffc8>] of_irq_init+0x14a/0x248
[    0.000000] [<ffffffff80600a7e>] start_kernel+0x40c/0x6fe
[    0.000000] [<ffffffff806034f6>] init_IRQ+0xc6/0x100
[    0.000000] [<ffffffff80600a7e>] start_kernel+0x40c/0x6fe
[    0.000000] Code: 0007 c319 9123 00e7 8082 000f 0140 411c 000f 0820 (c593) fff5 
[    0.000000] ---[ end trace 0000000000000000 ]---
[    0.000000] Kernel panic - not syncing: Fatal exception in interrupt

I guess I'm either using some unsupported configuration or making some
stupid mistakes, but I cannot find any documentation about how to
configure the mainline kernel for Lichee Pi 4A properly.  Could you give
some pointers?

And this line

Memory: 8145304K/8388608K available (4922K kernel code, 4786K rwdata, 2048K rodata, 2148K init, 393K bss, 243304K reserved, 0K cma-reserved)

does not match my hardware (my board is a 16 GB DRAM variant).  So in
the future we'll need multiple DTs for all the variants?

> NOTE: the thead cpu reset dt-binding and DT node are removed in v3. This
> makes secondary CPUs unable to be online. However, minimal th1520
> support is better than nothing. And the community has been working on
> and will work on the cpu reset dt-binding, for example, Conor, Guo and
> Jessica are discussing about it, I have seen valuable comments and
> inputs from them. I believe we can add back cpu reset in next
> development window.
> 
> Thanks
> 
> Since v2:
>   - remove thead cpu-rst dt-binding doc and its DT node from th1520.dtsi
>   - collect Reviewed-by and Acked-by tags
>   - update uart reg size as suggested by Yixun
>   - Add Guo Ren and Fu Wei as THEAD SoCs Maintainers
> 
> Since v1:
>   - add missing plic, clint, th1520 itself dt-bindings
>   - use c900-plic
>   - s/light/th1520
>   - add dt-binding for T-HEAD CPU reset
>   - enable ARCH_THEAD in defconfig
>   - fix all dtbs_check error/warning except the CPU RESET, see above.
> 
> Jisheng Zhang (8):
>   dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
>   dt-bindings: timer: Add T-HEAD TH1520 clint
>   dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
>   riscv: Add the T-HEAD SoC family Kconfig option
>   riscv: dts: add initial T-HEAD TH1520 SoC device tree
>   riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
>   MAINTAINERS: add entry for T-HEAD RISC-V SoC
>   riscv: defconfig: enable T-HEAD SoC
> 
>  .../sifive,plic-1.0.0.yaml                    |   1 +
>  .../devicetree/bindings/riscv/thead.yaml      |  29 ++
>  .../bindings/timer/sifive,clint.yaml          |   1 +
>  MAINTAINERS                                   |   8 +
>  arch/riscv/Kconfig.socs                       |   6 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/thead/Makefile            |   2 +
>  .../dts/thead/th1520-lichee-module-4a.dtsi    |  38 ++
>  .../boot/dts/thead/th1520-lichee-pi-4a.dts    |  32 ++
>  arch/riscv/boot/dts/thead/th1520.dtsi         | 422 ++++++++++++++++++
>  arch/riscv/configs/defconfig                  |   1 +
>  11 files changed, 541 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
>  create mode 100644 arch/riscv/boot/dts/thead/Makefile
>  create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
>  create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
>  create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
> 





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