On 26.07.2023 17:09:07, haibo.chen@xxxxxxx wrote:
> From: Haibo Chen <haibo.chen@xxxxxxx>
>
> imx93 A0 chip use the internal q-channel handshake signal in LPCG
> and CCM to automatically handle the Flex-CAN stop mode. But this
> method meet issue when do the system PM stress test. IC can't fix
> it easily. So in the new imx93 A1 chip, IC drop this method, and
> involve back the old way，use the GPR method to trigger the Flex-CAN
> stop mode signal. Now NXP claim to drop imx93 A0, and only support
> imx93 A1. So here add the stop mode through GPR.
>
> Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx93.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> index 4ec9df78f205..d2040019e9c7 100644
> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> @@ -319,6 +319,7 @@ flexcan1: can@443a0000 {
> assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> assigned-clock-rates = <40000000>;
> fsl,clk-source = /bits/ 8 <0>;
> + fsl,stop-mode = <&anomix_ns_gpr 0x14 0>;
I think there's a typo in the mainline imx93.dtsi. AFAICS it's supposed
to be "aonmix_ns_gpr", not "anomix_ns_gpr". But that's a different
problem to patch :)
AFAICS, according to imx93, rev2 data sheet, offset 0x14 is 76.6.1.3
QCHANNEL DISABLE (QCH_DIS) and bit 0 is "GPIO1". Are you sure this is
the correct reg?
> status = "disabled";
> };
>
> @@ -591,6 +592,7 @@ flexcan2: can@425b0000 {
> assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> assigned-clock-rates = <40000000>;
> fsl,clk-source = /bits/ 8 <0>;
> + fsl,stop-mode = <&wakeupmix_gpr 0x0C 2>;
looks plausible, please use lower case for hex addresses.
> status = "disabled";
> };
>
> --
> 2.34.1
>
>
regards,
Marc
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