Hi Marco, Thank you for the patch. On Mon, Jul 17, 2023 at 06:51:27PM +0200, Marco Felsch wrote: > Add support for the Debix SOM A + SOM A I/O board. The commit enables > only the basic features like: > - 2x UART > - 2x Network > - eMMC/µSD > - CAN > - QSPI > - USB Host / Device > > Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx> > --- > Required patchsets: > > - usb: https://lore.kernel.org/all/20230623142228.4069084-1-m.felsch@xxxxxxxxxxxxxx/ > - net: https://lore.kernel.org/all/20230717164307.2868264-1-m.felsch@xxxxxxxxxxxxxx/ > > Changelog: > > v2: > - drop to generic polyhex,imx8mp-debix binding > - net/phy: replace deprecated snps,reset-* and phy-reset-* bindings with > new phy-node based ones > - net/phy: fix phy properties and reset timings > - net/phy: add fec phy-supply handling > - net/phy: add eqos phy-supply handling > - net/phy: fix baseboard-vdd3v3 timings to fulfill net-phy-timings > - Fix spelling > - Drop superfluous blank lines > - pmic: make use of IRQ_TYPE_LEVEL_LOW > - pmic: add whitespace between buck node name and '{' > > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../freescale/imx8mp-debix-som-a-bmb-08.dts | 470 ++++++++++++++++++ > .../dts/freescale/imx8mp-debix-som-a.dtsi | 266 ++++++++++ > 3 files changed, 737 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index ef7d17aef58f0..ca7c9595e6ffa 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts > new file mode 100644 > index 0000000000000..17028ab169717 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts > @@ -0,0 +1,470 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2019 NXP > + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@xxxxxxxxxxxxxx> > + */ > + > +/dts-v1/; > + > +#include "imx8mp-debix-som-a.dtsi" > + > +/ { > + model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; > + compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", > + "fsl,imx8mp"; > + > + chosen { > + stdout-path = &uart2; > + }; > + > + reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "BB_VDD3V3"; > + gpio = <&expander0 10 GPIO_ACTIVE_HIGH>; > + /* Required timings for ethernet phy's */ > + startup-delay-us = <50000>; The regulator's datasheet shows a much smaller delay (about 1500µs with a 3A load). > + off-on-delay-us = <110000>; Is this really a property of the regulator ? Or a requirement of the ethernet PHY ? In the latter case, shouldn't it be handled by the PHY ? > + enable-active-high; > + regulator-always-on; Why always on ? Same for the other supplies. > + }; > + > + reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-name = "BB_VDD5V"; > + gpio = <&expander0 9 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + regulator-som-vdd1v8 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-name = "SOM_VDD1V8_SW"; > + gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + regulator-som-vdd3v3 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "SOM_VDD3V3_SW"; > + gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + regulator-name = "VSD_3V3"; This seems to be produced by the SoM, it should be moved to the SoM .dtsi. > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + regulator-vbus-usb20 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-name = "USB20_5V"; > + gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + vin-supply = <®_baseboard_vdd5v0>; > + }; > + > + regulator-vbus-usb30 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-name = "USB30_5V"; > + gpio = <&expander1 12 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + vin-supply = <®_baseboard_vdd5v0>; > + }; > + > + reg_vdd5v0: regulator-vdd5v0 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-name = "VDD_5V"; > + gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > +}; > + > +&eqos { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_eqos>; > + phy-supply = <®_baseboard_vdd3v3>; > + phy-handle = <ðphy0>; > + phy-mode = "rgmii-id"; > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@0 { Unless I'm mistaken, the PHYs are both at address 1. Address 0 works as it's the broadcast address, but is there a good reason not to use the real address ? Same below. > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; > + reset-assert-us = <20000>; > + reset-deassert-us = <150000>; > + eee-broken-1000t; > + realtek,clkout-disable; > + }; > + }; > +}; > + > +&fec { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec>; > + phy-supply = <®_baseboard_vdd3v3>; > + phy-handle = <ðphy1>; > + phy-mode = "rgmii-id"; > + fsl,magic-packet; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy1: ethernet-phy@0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; > + reset-assert-us = <20000>; > + reset-deassert-us = <150000>; > + eee-broken-1000t; > + realtek,clkout-disable; > + }; > + }; > +}; > + > +&flexcan1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + xceiver-supply = <®_vdd5v0>; > + status = "okay"; > +}; > + > +&flexcan2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan2>; > + xceiver-supply = <®_vdd5v0>; > + status = "okay"; > +}; > + > +&flexspi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexspi0>; > + status = "okay"; > + > + flash: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <80000000>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +}; > + > +&i2c4 { > + expander0: gpio@20 { > + compatible = "nxp,pca9535"; > + reg = <0x20>; > + gpio-controller; > + #gpio-cells = <0x02>; > + }; > + > + expander1: gpio@23 { > + compatible = "nxp,pca9535"; > + reg = <0x23>; > + gpio-controller; > + #gpio-cells = <0x02>; > + > + /* > + * Since USB1 is bound to peripheral mode we need to ensure > + * that VBUS is turned off. > + */ > + usb30-otg-hog { > + gpio-hog; > + gpios = <13 GPIO_ACTIVE_HIGH>; > + output-low; > + line-name = "USB30_OTG_EN"; > + }; > + }; > + > + eeprom@52 { > + compatible = "atmel,24c02"; > + reg = <0x52>; > + pagesize = <16>; > + }; > + > + rtc@51 { > + compatible = "haoyu,hym8563"; > + reg = <0x51>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rtc>; > + interrupt-parent = <&gpio4>; > + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; > + #clock-cells = <0>; > + }; > +}; > + > +&snvs_pwrkey { > + status = "okay"; > +}; > + > +/* Debug */ > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + status = "okay"; > +}; > + > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart4>; > + status = "okay"; > +}; > + > +&usb3_0 { > + status = "okay"; > +}; > + > +&usb3_1 { > + status = "okay"; > +}; > + > +&usb_dwc3_0 { > + dr_mode = "peripheral"; > + status = "okay"; > +}; > + > +&usb_dwc3_1 { > + dr_mode = "host"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + /* 2.x hub on port 1 */ > + usb_hub_2_x: hub@1 { > + compatible = "usb5e3,610"; > + reg = <1>; > + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; > + vdd-supply = <®_vdd5v0>; > + peer-hub = <&usb_hub_3_x>; > + }; > + > + /* 3.x hub on port 2 */ > + usb_hub_3_x: hub@2 { > + compatible = "usb5e3,620"; > + reg = <2>; > + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; > + vdd-supply = <®_vdd5v0>; > + peer-hub = <&usb_hub_2_x>; > + }; > +}; > + > +&usb3_phy0 { > + status = "okay"; > +}; > + > +&usb3_phy1 { > + status = "okay"; > +}; > + > +/* µSD Card */ > +&usdhc2 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; > + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; > + assigned-clock-rates = <400000000>; > + vmmc-supply = <®_usdhc2_vmmc>; > + bus-width = <4>; > + disable-wp; > + no-sdio; > + no-mmc; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_eqos: eqosgrp { > + fsl,pins = < > + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 > + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 > + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 > + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 > + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 > + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 > + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 > + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 > + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f > + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f > + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f > + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f > + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f > + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f > + > + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f > + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 > + >; > + }; > + > + pinctrl_fec: fecgrp { > + fsl,pins = < > + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 > + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 > + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 > + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 > + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 > + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 > + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 > + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 > + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f > + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f > + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f > + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f > + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f > + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f > + MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f > + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp { > + fsl,pins = < > + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 > + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 > + >; > + }; > + > + pinctrl_flexcan2: flexcan2grp { > + fsl,pins = < > + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 > + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 > + >; > + }; > + > + pinctrl_flexspi0: flexspi0grp { > + fsl,pins = < > + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 > + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 > + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 > + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 > + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 > + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 > + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 > + >; > + }; > + > + pinctrl_i2c4: i2c4grp { > + fsl,pins = < > + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 > + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_rtc: rtcgrp { > + fsl,pins = < > + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 > + >; > + }; > + > + pinctrl_pmic: pmicgrp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 > + >; > + }; > + > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > + fsl,pins = < > + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f > + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 > + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 > + >; > + }; > + > + pinctrl_uart4: uart4grp { > + fsl,pins = < > + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 > + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 > + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 > + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 > + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 > + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 > + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 > + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = < > + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 > + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 > + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 > + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 > + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 > + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 > + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = < > + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 > + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 > + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 > + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 > + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 > + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 > + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 > + >; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi > new file mode 100644 > index 0000000000000..a089cadacc105 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi > @@ -0,0 +1,266 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2019 NXP > + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@xxxxxxxxxxxxxx> > + */ > + > +#include "imx8mp.dtsi" > + > +/ { > + model = "Polyhex i.MX8MPlus Debix SOM A"; > + compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; > +}; > + > +&A53_0 { > + cpu-supply = <&buck2>; > +}; > + > +&A53_1 { > + cpu-supply = <&buck2>; > +}; > + > +&A53_2 { > + cpu-supply = <&buck2>; > +}; > + > +&A53_3 { > + cpu-supply = <&buck2>; > +}; > + > +&i2c1 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "okay"; > + > + pmic@25 { > + compatible = "nxp,pca9450c"; > + reg = <0x25>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio1>; > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > + > + regulators { > + buck1: BUCK1 { > + regulator-name = "BUCK1"; > + regulator-min-microvolt = <600000>; > + regulator-max-microvolt = <2187500>; > + regulator-boot-on; > + regulator-always-on; > + regulator-ramp-delay = <3125>; > + }; > + > + buck2: BUCK2 { > + regulator-name = "BUCK2"; > + regulator-min-microvolt = <600000>; > + regulator-max-microvolt = <2187500>; > + regulator-boot-on; > + regulator-always-on; > + regulator-ramp-delay = <3125>; > + nxp,dvs-run-voltage = <950000>; > + nxp,dvs-standby-voltage = <850000>; > + }; > + > + buck4: BUCK4 { > + regulator-name = "BUCK4"; > + regulator-min-microvolt = <600000>; > + regulator-max-microvolt = <3400000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck5: BUCK5 { > + regulator-name = "BUCK5"; > + regulator-min-microvolt = <600000>; > + regulator-max-microvolt = <3400000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck6: BUCK6 { > + regulator-name = "BUCK6"; > + regulator-min-microvolt = <600000>; > + regulator-max-microvolt = <3400000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo1: LDO1 { > + regulator-name = "LDO1"; > + regulator-min-microvolt = <1600000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo2: LDO2 { > + regulator-name = "LDO2"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1150000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo3: LDO3 { > + regulator-name = "LDO3"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo4: LDO4 { > + regulator-name = "LDO4"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo5: LDO5 { > + regulator-name = "LDO5"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + }; > + }; > +}; > + > +&i2c4 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c4>; > + status = "okay"; > + > + adc@48 { > + compatible = "ti,ads1115"; > + reg = <0x48>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + channel@4 { > + reg = <4>; > + ti,gain = <1>; > + ti,datarate = <7>; > + }; > + channel@5 { > + reg = <5>; > + ti,gain = <1>; > + ti,datarate = <7>; > + }; > + channel@6 { > + reg = <6>; > + ti,gain = <1>; > + ti,datarate = <7>; > + }; > + channel@7 { > + reg = <7>; > + ti,gain = <1>; > + ti,datarate = <7>; > + }; > + }; > +}; > + > +&snvs_pwrkey { > + status = "okay"; > +}; > + > +/* eMMC */ > +&usdhc3 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc3>; > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; > + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; > + assigned-clock-rates = <400000000>; > + bus-width = <8>; > + non-removable; > + status = "okay"; > +}; > + > +&wdog1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_wdog>; > + fsl,ext-reset-output; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 > + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 > + >; > + }; > + > + pinctrl_i2c4: i2c4grp { > + fsl,pins = < > + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 > + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_pmic: pmicgrp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 > + >; > + }; > + > + pinctrl_usdhc3: usdhc3grp { > + fsl,pins = < > + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 > + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 > + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 > + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 > + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 > + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 > + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 > + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 > + >; > + }; > + > + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { > + fsl,pins = < > + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 > + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 > + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 > + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 > + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 > + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 > + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 > + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 > + >; > + }; > + > + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > + fsl,pins = < > + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 > + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 > + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 > + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 > + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 > + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 > + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 > + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 > + >; > + }; > + > + pinctrl_wdog: wdoggrp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 > + >; > + }; > +}; -- Regards, Laurent Pinchart
