On 19/07/2023 04:55, Meng Li wrote: > Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2 > implementation, because the Stratix DWC2 implementation does > not support clock gating. This compatible is used with generic > snps,dwc2. > > Signed-off-by: Meng Li <Meng.Li@xxxxxxxxxxxxx> Missing changelog, missing versioning. This is v3 or v4. > --- > Documentation/devicetree/bindings/usb/dwc2.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml > index dc4988c0009c..f90094320914 100644 > --- a/Documentation/devicetree/bindings/usb/dwc2.yaml > +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml > @@ -51,6 +51,7 @@ properties: > - amlogic,meson-g12a-usb > - amlogic,meson-a1-usb > - intel,socfpga-agilex-hsotg > + - intel,socfpga-stratix10-hsotg So you just sent the same patch as before. I pointed you to the proper solution with compatibility. Best regards, Krzysztof
