Hey Xingyu, On Mon, Jul 17, 2023 at 10:30:33AM +0800, Xingyu Wu wrote: > This patch serises are to add PLL clocks driver and providers by writing > and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add > documentation and nodes to describe StarFive System Controller(syscon) > Registers. This patch serises are based on Linux 6.4. > > PLLs are high speed, low jitter frequency synthesizers in JH7110. > Each PLL clock works in integer mode or fraction mode by some dividers, > and the dividers are set in several syscon registers. > The formula for calculating frequency is: > Fvco = Fref * (NI + NF) / M / Q1 > > The first patch adds docunmentation to describe PLL clock bindings, > and the second patch adds documentation to decribe syscon registers. > The patch 3 modifies the SYSCRG bindings and adds PLL clock inputs. > The patch 4 adds driver to support PLL clocks for JH7110. > The patch 5 modifies the system clock driver and can select the PLL clock > source from PLL clocks driver. And the patch 6 adds the > stg/sys/aon syscon nodes for JH7110 SoC. The last patch modifies the > syscrg node in JH7110 dts file. Just FYI, I have picked up the binding & clock portions of this series and your other one adding the stg syscon. I've pushed them out here for the test robots to have a look: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=clk-starfive If that passes, my plan is to send Stephen a PR for the lot, later this week. Thanks, Conor.
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