The VSC8531 and similar PHYs (i.e. VSC8530, VSC8531, VSC8540 & VSC8541) have a CLKOUT pin on the chip that can be controlled by register (13G in the General Purpose Registers page) that can be configured to output a frequency of 25, 50 or 125 Mhz. This is useful when wanting to provide a clock source for the MAC in some board designs. Signed-off-by: Marius Muresan <marius.muresan@xxxxxx> Signed-off-by: Alexandru Ardelean <alex@xxxxxxxxxxx> --- Changelog v1 -> v2: * https://lore.kernel.org/netdev/20230706081554.1616839-1-alex@xxxxxxxxxxx/ * changed property name 'vsc8531,clkout-freq-mhz' -> 'mscc,clkout-freq-mhz' as requested by Rob * introduced 'goto set_reg' to reduce indentation (no idea why I did not think of that sooner) * added 'net-next' tag as requested by Andrew drivers/net/phy/mscc/mscc.h | 5 ++++ drivers/net/phy/mscc/mscc_main.c | 41 ++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 7a962050a4d4..4ea21921a7ba 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -181,6 +181,11 @@ enum rgmii_clock_delay { #define VSC8502_RGMII_TX_DELAY_MASK 0x0007 #define VSC8502_RGMII_RX_CLK_DISABLE 0x0800 +/* CKLOUT Control register, for VSC8531 and similar */ +#define VSC8531_CLKOUT_CNTL 13 +#define VSC8531_CLKOUT_CNTL_ENABLE BIT(15) +#define VSC8531_CLKOUT_CNTL_FREQ_MASK GENMASK(14, 13) + #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21 #define MSCC_PHY_WOL_MID_MAC_ADDR 22 #define MSCC_PHY_WOL_UPPER_MAC_ADDR 23 diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 4171f01d34e5..ec029d26071d 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -618,6 +618,42 @@ static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); } +static int vsc8531_clkout_config(struct phy_device *phydev) +{ + static const u32 freq_vals[] = { 25, 50, 125 }; + struct device *dev = &phydev->mdio.dev; + u16 mask, set; + u32 freq, i; + int rc; + + mask = VSC8531_CLKOUT_CNTL_ENABLE | VSC8531_CLKOUT_CNTL_FREQ_MASK; + set = 0; + + if (device_property_read_u32(dev, "mscc,clkout-freq-mhz", &freq)) + goto set_reg; + + /* The indices from 'freq_vals' are used in the register */ + for (i = 0; i < ARRAY_SIZE(freq_vals); i++) { + if (freq != freq_vals[i]) + continue; + + set |= VSC8531_CLKOUT_CNTL_ENABLE | + FIELD_PREP(VSC8531_CLKOUT_CNTL_FREQ_MASK, i); + break; + } + if (set == 0) + dev_warn(dev, "Invalid 'mscc,clkout-freq-mhz' value %u\n", + freq); + +set_reg: + mutex_lock(&phydev->lock); + rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO, + VSC8531_CLKOUT_CNTL, mask, set); + mutex_unlock(&phydev->lock); + + return rc; +} + static int vsc8531_pre_init_seq_set(struct phy_device *phydev) { int rc; @@ -1852,6 +1888,11 @@ static int vsc85xx_config_init(struct phy_device *phydev) rc = vsc8531_pre_init_seq_set(phydev); if (rc) return rc; + + rc = vsc8531_clkout_config(phydev); + if (rc) + return rc; + } rc = vsc85xx_eee_init_seq_set(phydev); -- 2.41.0
