Hi Prabhakar, > -----Original Message----- > From: Prabhakar <prabhakar.csengg@xxxxxxxxx> > Sent: Friday, June 30, 2023 1:05 PM > To: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; Magnus Damm > <magnus.damm@xxxxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@xxxxxxxxxx>; Linus Walleij > <linus.walleij@xxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; linux-gpio@xxxxxxxxxxxxxxx; Biju Das > <biju.das.jz@xxxxxxxxxxxxxx>; Prabhakar <prabhakar.csengg@xxxxxxxxx>; > Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in > RZG2L_GPIO_PORT_PACK() macro > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Currently we assume all the port pins are sequential ie always PX_0 to > PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to > P28_5 which have holes in them, for example only one pin on port19 is > available and that is P19_1 and not P19_0. > > So to handle such cases include pinmap for each port which would > indicate the pin availability on each port. With this we also get > additional pin validation, for example on the RZ/G2L SOC P0 has two pins > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7. > > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to > validate the gpio pin. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------ > 1 file changed, 86 insertions(+), 81 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 9511d920565e..a0c2e585e765 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -67,10 +67,12 @@ > PIN_CFG_FILCLKSEL) > > /* > - * n indicates number of pins in the port, a is the register index > - * and f is pin configuration capabilities supported. > + * m indicates the bitmap of supported pins, n indicates number > + * of pins in the port, a is the register index and f is pin > + * configuration capabilities supported. > */ > -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | > (f)) > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28) > | ((a) << 20) | (f)) > +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39, 32)) >> 32) > #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) > #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) > #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) > @@ -129,7 +131,7 @@ struct rzg2l_dedicated_configs { > > struct rzg2l_pinctrl_data { > const char * const *port_pins; > - const u32 *port_pin_configs; > + const u64 *port_pin_configs; Can this be SoC specific? Only for RZ/Five you need this changes. Others SoCs like RZ/{G2L,G2LC,V2L and G2UL) still work with u32* as there is no holes. With this change memory usage is doubled as we change from u32->u64. Cheers, Biju > unsigned int n_ports; > struct rzg2l_dedicated_configs *dedicated_pins; > unsigned int n_port_pins; > @@ -445,13 +447,16 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev > *pctldev, } > > static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, > - u32 cfg, u32 port, u8 bit) > + u64 cfg, u32 port, u8 bit) > { > - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); > u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); > - u32 data; > + u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg); > + u64 data; > > - if (bit >= pincount || port >= pctrl->data->n_port_pins) > + if (port >= pctrl->data->n_port_pins) > + return -EINVAL; > + > + if (!(pinmap & BIT(bit))) > return -EINVAL; > > data = pctrl->data->port_pin_configs[port]; > @@ -501,7 +506,7 @@ static int rzg2l_pinctrl_pinconf_get(struct > pinctrl_dev *pctldev, > struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); > enum pin_config_param param = pinconf_to_config_param(*config); > const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; > - unsigned int *pin_data = pin->drv_data; > + u64 *pin_data = pin->drv_data; > unsigned int arg = 0; > unsigned long flags; > void __iomem *addr; > @@ -591,7 +596,7 @@ static int rzg2l_pinctrl_pinconf_set(struct > pinctrl_dev *pctldev, { > struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); > const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; > - unsigned int *pin_data = pin->drv_data; > + u64 *pin_data = pin->drv_data; > enum pin_config_param param; > unsigned long flags; > void __iomem *addr; > @@ -965,78 +970,78 @@ static const char * const rzg2l_gpio_names[] = { > "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", > "P48_7", }; > > -static const u32 rzg2l_gpio_configs[] = { > - RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x24, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x25, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x26, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x27, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x28, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x29, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x2a, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x2b, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x2c, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(2, 0x2d, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x2e, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x2f, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x30, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x31, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x32, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x33, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x34, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(3, 0x35, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), > +static const u64 rzg2l_gpio_configs[] = { > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x10, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x11, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x12, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x13, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x14, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x15, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x16, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x17, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x18, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x19, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1a, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1b, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1d, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1e, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1f, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x21, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x22, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x23, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x24, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x25, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x26, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x27, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x28, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x29, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2a, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2b, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2c, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2d, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2e, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2f, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x30, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x31, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x32, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x33, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x34, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x35, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x36, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x37, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x38, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x39, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x3a, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3b, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3c, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3d, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3e, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3f, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x40, RZG2L_MPXED_PIN_FUNCS), > }; > > -static const u32 r9a07g043_gpio_configs[] = { > - RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(5, 0x11, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(4, 0x12, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(4, 0x13, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(6, 0x14, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > - RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(5, 0x17, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(5, 0x18, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(4, 0x19, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(5, 0x1a, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > - RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), > - RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), > +static const u64 r9a07g043_gpio_configs[] = { > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a, > RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS), > + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS), > }; > > static struct { > @@ -1396,7 +1401,7 @@ static int rzg2l_pinctrl_register(struct > rzg2l_pinctrl *pctrl) { > struct pinctrl_pin_desc *pins; > unsigned int i, j; > - u32 *pin_data; > + u64 *pin_data; > int ret; > > pctrl->desc.name = DRV_NAME; > -- > 2.34.1