Hello Neil,
Thank you for the review!
On Mon, Jun 26, 2023 at 03:36:23PM +0200, neil.armstrong@xxxxxxxxxx wrote:
> Hi,
>
> On 25/06/2023 23:11, Martin Blumenstingl wrote:
> > On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> wrote:
> > >
> > > From: Jan Dakinevich <yvdakinevich@xxxxxxxxxxxxxx>
> > >
> > > The definition is inspired by a similar one for AXG SoC family.
> > > 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
> > > "default" and "clk-gate" in board-specific device trees.
> > Let's wait for Neil's response on the other patch for the question
> > about pin mux settings
> >
> > > 'meson-gx' driver during initialization sets clock to safe low-frequency
> > > value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
> > > high-frequency by default, and using of eMMC's internal divider is not
> > > enough to achieve so low values. To provide low-frequency source,
> > > reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.
> > Even if the pinctrl part should be postponed then I think it's worth
> > adding &sd_emmc
>
> Yeah it's weird to add HW definition and to not enable them,
> so please enable them in the board if you add them in the DTSI.
Unfortunately, I'm unable to provide our internal board DTS. However, I
have an AD401 reference board on hand, so it's possible to test
everything there. I'll include these changes in the next version.
--
Thank you,
Dmitry
