On 27.06.2023 22:14, Marijn Suijten wrote:
> SM6125 features only a single PHY (despite a secondary PHY PLL source
> being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream
> sources for this "trinket" SoC do not define the typical "vcca"
> regulator to be available nor used. This, including the register offset
> is identical to QCM2290, whose config struct can trivially be reused.
>
> Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 9d5795c58a98..05621e5e7d63 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> .data = &dsi_phy_14nm_660_cfgs },
> { .compatible = "qcom,dsi-phy-14nm-8953",
> .data = &dsi_phy_14nm_8953_cfgs },
> + { .compatible = "qcom,sm6125-dsi-phy-14nm",
> + .data = &dsi_phy_14nm_2290_cfgs },
> #endif
> #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
> { .compatible = "qcom,dsi-phy-10nm",
>
