With the ICE driver now merged let's convert the ufs node to use the new
style.
Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 5cd7296c7660..79627117a776 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4120,9 +4120,7 @@ system-cache-controller@19200000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>,
- <0 0x01d88000 0 0x8000>;
- reg-names = "std", "ice";
+ reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -4147,8 +4145,7 @@ ufs_mem_hc: ufshc@1d84000 {
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk",
- "ice_core_clk";
+ "rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -4157,8 +4154,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
- <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
@@ -4167,8 +4163,9 @@ ufs_mem_hc: ufshc@1d84000 {
<75000000 300000000>,
<0 0>,
<0 0>,
- <0 0>,
- <75000000 300000000>;
+ <0 0>;
+ qcom,ice = <&ice>;
+
status = "disabled";
};
@@ -4198,6 +4195,13 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ ice: crypto@1d88000 {
+ compatible = "qcom,sm8450-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0 0x01d88000 0 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x28000>;
--
2.41.0
