On Wed, Jun 21, 2023 at 10:34:04AM -0700, Lizhi Hou wrote: > This patch series introduces OF overlay support for PCI devices which > primarily addresses two use cases. First, it provides a data driven method > to describe hardware peripherals that are present in a PCI endpoint and > hence can be accessed by the PCI host. Second, it allows reuse of a OF > compatible driver -- often used in SoC platforms -- in a PCI host based > system. > > There are 2 series devices rely on this patch: > > 1) Xilinx Alveo Accelerator cards (FPGA based device) > 2) Microchip LAN9662 Ethernet Controller > > Please see: https://lore.kernel.org/lkml/20220427094502.456111-1-clement.leger@xxxxxxxxxxx/ > > Normally, the PCI core discovers PCI devices and their BARs using the > PCI enumeration process. However, the process does not provide a way to > discover the hardware peripherals that are present in a PCI device, and > which can be accessed through the PCI BARs. Also, the enumeration process > does not provide a way to associate MSI-X vectors of a PCI device with the > hardware peripherals that are present in the device. PCI device drivers > often use header files to describe the hardware peripherals and their > resources as there is no standard data driven way to do so. This patch > series proposes to use flattened device tree blob to describe the > peripherals in a data driven way. Based on previous discussion, using > device tree overlay is the best way to unflatten the blob and populate > platform devices. To use device tree overlay, there are three obvious > problems that need to be resolved. > > First, we need to create a base tree for non-DT system such as x86_64. A > patch series has been submitted for this: > https://lore.kernel.org/lkml/20220624034327.2542112-1-frowand.list@xxxxxxxxx/ > https://lore.kernel.org/lkml/20220216050056.311496-1-lizhi.hou@xxxxxxxxxx/ > > Second, a device tree node corresponding to the PCI endpoint is required > for overlaying the flattened device tree blob for that PCI endpoint. > Because PCI is a self-discoverable bus, a device tree node is usually not > created for PCI devices. This series adds support to generate a device > tree node for a PCI device which advertises itself using PCI quirks > infrastructure. > > Third, we need to generate device tree nodes for PCI bridges since a child > PCI endpoint may choose to have a device tree node created. > > This patch series is made up of three patches. > > The first patch is adding OF interface to create or destroy OF node > dynamically. > > The second patch introduces a kernel option, CONFIG_DYNAMIC_PCI_OF_NODEX. In case this log becomes part of the merge commit or something, s/CONFIG_DYNAMIC_PCI_OF_NODEX/CONFIG_PCI_DYNAMIC_OF_NODES/ > When the option is turned on, the kernel will generate device tree nodes > for all PCI bridges unconditionally. The patch also shows how to use the > PCI quirks infrastructure, DECLARE_PCI_FIXUP_FINAL to generate a device > tree node for a device. Specifically, the patch generates a device tree > node for Xilinx Alveo U50 PCIe accelerator device. The generated device > tree nodes do not have any property. > > The third patch adds basic properties ('reg', 'compatible' and > 'device_type') to the dynamically generated device tree nodes. More > properties can be added in the future. > > Here is the example of device tree nodes generated within the ARM64 QEMU. It's not obvious to me what was there originally and what was added because of this series. > # lspci -t > -[0000:00]-+-00.0 > +-01.0 > +-03.0-[01-03]----00.0-[02-03]----00.0-[03]----00.0 > +-03.1-[04]-- > \-04.0-[05-06]----00.0-[06]-- > # tree /sys/firmware/devicetree/base/pcie\@10000000 > /sys/firmware/devicetree/base/pcie@10000000 > |-- #address-cells > |-- #interrupt-cells > |-- #size-cells > |-- bus-range > |-- compatible > |-- device_type > |-- dma-coherent > |-- interrupt-map > |-- interrupt-map-mask > |-- linux,pci-domain > |-- msi-map > |-- name > |-- pci@3,0 > | |-- #address-cells > | |-- #size-cells > | |-- compatible > | |-- device_type > | |-- pci@0,0 > | | |-- #address-cells > | | |-- #size-cells > | | |-- compatible > | | |-- device_type > | | |-- pci@0,0 > | | | |-- #address-cells > | | | |-- #size-cells > | | | |-- compatible > | | | |-- dev@0,0 > | | | | |-- #address-cells > | | | | |-- #size-cells > | | | | |-- compatible > | | | | |-- ranges > | | | | `-- reg > | | | |-- device_type > | | | |-- ranges > | | | `-- reg > | | |-- ranges > | | `-- reg > | |-- ranges > | `-- reg > |-- pci@3,1 > | |-- #address-cells > | |-- #size-cells > | |-- compatible > | |-- device_type > | |-- ranges > | `-- reg > |-- pci@4,0 > | |-- #address-cells > | |-- #size-cells > | |-- compatible > | |-- device_type > | |-- pci@0,0 > | | |-- #address-cells > | | |-- #size-cells > | | |-- compatible > | | |-- device_type > | | |-- ranges > | | `-- reg > | |-- ranges > | `-- reg > |-- ranges > `-- reg
