Hello Rob, > -----Original Message----- > From: Rob Herring <robh@xxxxxxxxxx> > Sent: Friday, June 16, 2023 8:56 PM > To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@xxxxxxx> > Cc: tudor.ambarus@xxxxxxxxxx; pratyush@xxxxxxxxxx; > miquel.raynal@xxxxxxxxxxx; richard@xxxxxx; vigneshr@xxxxxx; > krzysztof.kozlowski+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; git (AMD-Xilinx) > <git@xxxxxxx>; michael@xxxxxxxx; linux-mtd@xxxxxxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > amitrkcian2002@xxxxxxxxx > Subject: Re: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property > to avoid setting SRWD bit in status register > > On Fri, Jun 16, 2023 at 02:25:12PM +0530, Amit Kumar Mahapatra wrote: > > If the WP signal of the flash device is not connected and the software > > sets the status register write disable (SRWD) bit in the status > > register then thestatus register permanently becomes read-only. To > > avoid this added a new boolean DT property "broken-wp". If WP signal > > is not connected, then this property should be set in the DT to avoid > > setting the SRWD during status register write operation. > > > > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xxxxxxx> > > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > --- > > .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > > b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > > index 89959e5c47ba..10a6df752f6f 100644 > > --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > > +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > > @@ -70,6 +70,21 @@ properties: > > be used on such systems, to denote the absence of a reliable reset > > mechanism. > > > > + broken-wp: > > In the tied low case, that's designed behavior rather than broken. The name > should reflect that. In that case will it be ok to change it to "no-wp". Please let me know if you have any other suitable name. Regards, Amit > > > + type: boolean > > + description: > > + The status register write disable (SRWD) bit in status register, combined > > + with the WP signal, provides hardware data protection for the device. > When > > + the SRWD bit is set to 1, and the WP signal is either driven LOW or hard > > + strapped to LOW, the status register nonvolatile bits become read-only > and > > + the WRITE STATUS REGISTER operation will not execute. The only way > to exit > > + this hardware-protected mode is to drive WP HIGH. If the WP signal of > the > > + flash device is not connected then status register permanently becomes > > + read-only as the SRWD bit cannot be reset. This boolean flag can be > used > > + on systems in which WP signal is not connected, to avoid setting the > SRWD > > + bit while writing the status register. If the WP signal is hard strapped > > + to LOW then it is not broken as it can be a valid use case. > > + > > reset-gpios: > > description: > > A GPIO line connected to the RESET (active low) signal of the device. > > -- > > 2.17.1 > >
