On Fri, Jun 9, 2023 at 8:07 AM Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> wrote: > > Cleanup bindings dropping unneeded quotes. Once all these are fixed, > checking for this can be enabled in yamllint. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Note that I already have the whole tree done. Just not all split up. Acked-by: Rob Herring <robh@xxxxxxxxxx> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index db5253a2a74a..8a56473cdd5a 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -61,7 +61,7 @@ properties: > hart. These values originate from the RISC-V Privileged > Specification document, available from > https://riscv.org/specifications/ > - $ref: "/schemas/types.yaml#/definitions/string" > + $ref: /schemas/types.yaml#/definitions/string > enum: > - riscv,sv32 > - riscv,sv39 > @@ -95,7 +95,7 @@ properties: > While the isa strings in ISA specification are case > insensitive, letters in the riscv,isa string must be all > lowercase. > - $ref: "/schemas/types.yaml#/definitions/string" > + $ref: /schemas/types.yaml#/definitions/string > pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ > > # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here > @@ -120,7 +120,7 @@ properties: > - interrupt-controller > > cpu-idle-states: > - $ref: '/schemas/types.yaml#/definitions/phandle-array' > + $ref: /schemas/types.yaml#/definitions/phandle-array > items: > maxItems: 1 > description: | > -- > 2.34.1 >
