On Thu, Jun 8, 2023 at 4:57 AM Nícolas F. R. A. Prado
<nfraprado@xxxxxxxxxxxxx> wrote:
>
> Add the CLK_VDEC_ACTIVE clock to the vdec clock driver. This clock is
> enabled by the VPU once it starts decoding.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
>
> ---
>
> Changes in v2:
> - Added CLK_IGNORE_UNUSED flag
>
> drivers/clk/mediatek/clk-mt8183-vdec.c | 5 +++++
> include/dt-bindings/clock/mt8183-clk.h | 3 ++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/clk-mt8183-vdec.c
> index 513b7956cbea..03c4f1acfdb8 100644
> --- a/drivers/clk/mediatek/clk-mt8183-vdec.c
> +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c
> @@ -27,6 +27,10 @@ static const struct mtk_gate_regs vdec1_cg_regs = {
> GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
> &mtk_clk_gate_ops_setclr_inv)
>
> +#define GATE_VDEC0(_id, _name, _parent, _shift) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &vdec0_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED)
I think what you want is a read-only gate clock only used for reading back
the status. The ops would only have .is_enabled.
ChenYu
