The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_eeclkc_data struct to finally get rid on the
NR_CLKS define.
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
drivers/clk/meson/axg.c | 281 ++++----
drivers/clk/meson/axg.h | 2 -
drivers/clk/meson/g12a.c | 1481 +++++++++++++++++++--------------------
drivers/clk/meson/g12a.h | 2 -
drivers/clk/meson/gxbb.c | 842 +++++++++++-----------
drivers/clk/meson/gxbb.h | 2 -
drivers/clk/meson/meson-eeclk.c | 22 +-
drivers/clk/meson/meson-eeclk.h | 3 +-
8 files changed, 1312 insertions(+), 1323 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 2ad3801398dc..d159b47c7579 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -1890,147 +1890,143 @@ static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
/* Array of all clocks provided by this provider */
-static struct clk_hw_onecell_data axg_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &axg_sys_pll.hw,
- [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
- [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
- [CLKID_CLK81] = &axg_clk81.hw,
- [CLKID_MPLL0] = &axg_mpll0.hw,
- [CLKID_MPLL1] = &axg_mpll1.hw,
- [CLKID_MPLL2] = &axg_mpll2.hw,
- [CLKID_MPLL3] = &axg_mpll3.hw,
- [CLKID_DDR] = &axg_ddr.hw,
- [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
- [CLKID_ISA] = &axg_isa.hw,
- [CLKID_PL301] = &axg_pl301.hw,
- [CLKID_PERIPHS] = &axg_periphs.hw,
- [CLKID_SPICC0] = &axg_spicc_0.hw,
- [CLKID_I2C] = &axg_i2c.hw,
- [CLKID_RNG0] = &axg_rng0.hw,
- [CLKID_UART0] = &axg_uart0.hw,
- [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
- [CLKID_SPICC1] = &axg_spicc_1.hw,
- [CLKID_PCIE_A] = &axg_pcie_a.hw,
- [CLKID_PCIE_B] = &axg_pcie_b.hw,
- [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
- [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
- [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
- [CLKID_DMA] = &axg_dma.hw,
- [CLKID_SPI] = &axg_spi.hw,
- [CLKID_AUDIO] = &axg_audio.hw,
- [CLKID_ETH] = &axg_eth_core.hw,
- [CLKID_UART1] = &axg_uart1.hw,
- [CLKID_G2D] = &axg_g2d.hw,
- [CLKID_USB0] = &axg_usb0.hw,
- [CLKID_USB1] = &axg_usb1.hw,
- [CLKID_RESET] = &axg_reset.hw,
- [CLKID_USB] = &axg_usb_general.hw,
- [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
- [CLKID_EFUSE] = &axg_efuse.hw,
- [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
- [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
- [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
- [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
- [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
- [CLKID_GIC] = &axg_gic.hw,
- [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &axg_ao_iface.hw,
- [CLKID_AO_I2C] = &axg_ao_i2c.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
- [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
- [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
- [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
- [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
- [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
- [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
- [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
- [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
- [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
- [CLKID_GEN_CLK] = &axg_gen_clk.hw,
- [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
- [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
- [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
- [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
- [CLKID_VPU_0] = &axg_vpu_0.hw,
- [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
- [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
- [CLKID_VPU_1] = &axg_vpu_1.hw,
- [CLKID_VPU] = &axg_vpu.hw,
- [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
- [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
- [CLKID_VAPB_0] = &axg_vapb_0.hw,
- [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
- [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
- [CLKID_VAPB_1] = &axg_vapb_1.hw,
- [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
- [CLKID_VAPB] = &axg_vapb.hw,
- [CLKID_VCLK] = &axg_vclk.hw,
- [CLKID_VCLK2] = &axg_vclk2.hw,
- [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
- [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
- [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
- [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
- [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
- [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
- [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
- [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *axg_hw_clks[] = {
+ [CLKID_SYS_PLL] = &axg_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &axg_clk81.hw,
+ [CLKID_MPLL0] = &axg_mpll0.hw,
+ [CLKID_MPLL1] = &axg_mpll1.hw,
+ [CLKID_MPLL2] = &axg_mpll2.hw,
+ [CLKID_MPLL3] = &axg_mpll3.hw,
+ [CLKID_DDR] = &axg_ddr.hw,
+ [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
+ [CLKID_ISA] = &axg_isa.hw,
+ [CLKID_PL301] = &axg_pl301.hw,
+ [CLKID_PERIPHS] = &axg_periphs.hw,
+ [CLKID_SPICC0] = &axg_spicc_0.hw,
+ [CLKID_I2C] = &axg_i2c.hw,
+ [CLKID_RNG0] = &axg_rng0.hw,
+ [CLKID_UART0] = &axg_uart0.hw,
+ [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
+ [CLKID_SPICC1] = &axg_spicc_1.hw,
+ [CLKID_PCIE_A] = &axg_pcie_a.hw,
+ [CLKID_PCIE_B] = &axg_pcie_b.hw,
+ [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
+ [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
+ [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
+ [CLKID_DMA] = &axg_dma.hw,
+ [CLKID_SPI] = &axg_spi.hw,
+ [CLKID_AUDIO] = &axg_audio.hw,
+ [CLKID_ETH] = &axg_eth_core.hw,
+ [CLKID_UART1] = &axg_uart1.hw,
+ [CLKID_G2D] = &axg_g2d.hw,
+ [CLKID_USB0] = &axg_usb0.hw,
+ [CLKID_USB1] = &axg_usb1.hw,
+ [CLKID_RESET] = &axg_reset.hw,
+ [CLKID_USB] = &axg_usb_general.hw,
+ [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
+ [CLKID_EFUSE] = &axg_efuse.hw,
+ [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
+ [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
+ [CLKID_GIC] = &axg_gic.hw,
+ [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &axg_ao_iface.hw,
+ [CLKID_AO_I2C] = &axg_ao_i2c.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
+ [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
+ [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
+ [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
+ [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
+ [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
+ [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
+ [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
+ [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &axg_gen_clk.hw,
+ [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
+ [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
+ [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
+ [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
+ [CLKID_VPU_0] = &axg_vpu_0.hw,
+ [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
+ [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
+ [CLKID_VPU_1] = &axg_vpu_1.hw,
+ [CLKID_VPU] = &axg_vpu.hw,
+ [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
+ [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
+ [CLKID_VAPB_0] = &axg_vapb_0.hw,
+ [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
+ [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
+ [CLKID_VAPB_1] = &axg_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
+ [CLKID_VAPB] = &axg_vapb.hw,
+ [CLKID_VCLK] = &axg_vclk.hw,
+ [CLKID_VCLK2] = &axg_vclk2.hw,
+ [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
+ [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
+ [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
+ [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
+ [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
+ [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
+ [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
+ [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
};
/* Convenience table to populate regmap in .probe */
@@ -2163,7 +2159,8 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
static const struct meson_eeclkc_data axg_clkc_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
- .hw_onecell_data = &axg_hw_onecell_data,
+ .hw_clks = axg_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(axg_hw_clks),
};
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 23ea87964af2..39f9e2db82bd 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -160,8 +160,6 @@
#define CLKID_VDIN_MEAS_SEL 134
#define CLKID_VDIN_MEAS_DIV 135
-#define NR_CLKS 137
-
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 310accf94830..ee1ac3542ff4 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -4244,746 +4244,734 @@ static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
/* Array of all clocks provided by this provider */
-static struct clk_hw_onecell_data g12a_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
- [CLKID_CLK81] = &g12a_clk81.hw,
- [CLKID_MPLL0] = &g12a_mpll0.hw,
- [CLKID_MPLL1] = &g12a_mpll1.hw,
- [CLKID_MPLL2] = &g12a_mpll2.hw,
- [CLKID_MPLL3] = &g12a_mpll3.hw,
- [CLKID_DDR] = &g12a_ddr.hw,
- [CLKID_DOS] = &g12a_dos.hw,
- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
- [CLKID_ISA] = &g12a_isa.hw,
- [CLKID_PL301] = &g12a_pl301.hw,
- [CLKID_PERIPHS] = &g12a_periphs.hw,
- [CLKID_SPICC0] = &g12a_spicc_0.hw,
- [CLKID_I2C] = &g12a_i2c.hw,
- [CLKID_SANA] = &g12a_sana.hw,
- [CLKID_SD] = &g12a_sd.hw,
- [CLKID_RNG0] = &g12a_rng0.hw,
- [CLKID_UART0] = &g12a_uart0.hw,
- [CLKID_SPICC1] = &g12a_spicc_1.hw,
- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
- [CLKID_AUDIO] = &g12a_audio.hw,
- [CLKID_ETH] = &g12a_eth_core.hw,
- [CLKID_DEMUX] = &g12a_demux.hw,
- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
- [CLKID_ADC] = &g12a_adc.hw,
- [CLKID_UART1] = &g12a_uart1.hw,
- [CLKID_G2D] = &g12a_g2d.hw,
- [CLKID_RESET] = &g12a_reset.hw,
- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
- [CLKID_PARSER] = &g12a_parser.hw,
- [CLKID_USB] = &g12a_usb_general.hw,
- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
- [CLKID_BT656] = &g12a_bt656.hw,
- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
- [CLKID_UART2] = &g12a_uart2.hw,
- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
- [CLKID_GIC] = &g12a_gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
- [CLKID_IEC958] = &g12a_iec958_gate.hw,
- [CLKID_ENC480P] = &g12a_enc480p.hw,
- [CLKID_RNG1] = &g12a_rng1.hw,
- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
- [CLKID_DMA] = &g12a_dma.hw,
- [CLKID_EFUSE] = &g12a_efuse.hw,
- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
- [CLKID_VPU_0] = &g12a_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
- [CLKID_VPU_1] = &g12a_vpu_1.hw,
- [CLKID_VPU] = &g12a_vpu.hw,
- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
- [CLKID_VAPB] = &g12a_vapb.hw,
- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
- [CLKID_VCLK] = &g12a_vclk.hw,
- [CLKID_VCLK2] = &g12a_vclk2.hw,
- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
- [CLKID_HDMI] = &g12a_hdmi.hw,
- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
- [CLKID_MALI_0] = &g12a_mali_0.hw,
- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
- [CLKID_MALI_1] = &g12a_mali_1.hw,
- [CLKID_MALI] = &g12a_mali.hw,
- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
- [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
- [CLKID_TS_DIV] = &g12a_ts_div.hw,
- [CLKID_TS] = &g12a_ts.hw,
- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
-};
-
-static struct clk_hw_onecell_data g12b_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
- [CLKID_CLK81] = &g12a_clk81.hw,
- [CLKID_MPLL0] = &g12a_mpll0.hw,
- [CLKID_MPLL1] = &g12a_mpll1.hw,
- [CLKID_MPLL2] = &g12a_mpll2.hw,
- [CLKID_MPLL3] = &g12a_mpll3.hw,
- [CLKID_DDR] = &g12a_ddr.hw,
- [CLKID_DOS] = &g12a_dos.hw,
- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
- [CLKID_ISA] = &g12a_isa.hw,
- [CLKID_PL301] = &g12a_pl301.hw,
- [CLKID_PERIPHS] = &g12a_periphs.hw,
- [CLKID_SPICC0] = &g12a_spicc_0.hw,
- [CLKID_I2C] = &g12a_i2c.hw,
- [CLKID_SANA] = &g12a_sana.hw,
- [CLKID_SD] = &g12a_sd.hw,
- [CLKID_RNG0] = &g12a_rng0.hw,
- [CLKID_UART0] = &g12a_uart0.hw,
- [CLKID_SPICC1] = &g12a_spicc_1.hw,
- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
- [CLKID_AUDIO] = &g12a_audio.hw,
- [CLKID_ETH] = &g12a_eth_core.hw,
- [CLKID_DEMUX] = &g12a_demux.hw,
- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
- [CLKID_ADC] = &g12a_adc.hw,
- [CLKID_UART1] = &g12a_uart1.hw,
- [CLKID_G2D] = &g12a_g2d.hw,
- [CLKID_RESET] = &g12a_reset.hw,
- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
- [CLKID_PARSER] = &g12a_parser.hw,
- [CLKID_USB] = &g12a_usb_general.hw,
- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
- [CLKID_BT656] = &g12a_bt656.hw,
- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
- [CLKID_UART2] = &g12a_uart2.hw,
- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
- [CLKID_GIC] = &g12a_gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
- [CLKID_IEC958] = &g12a_iec958_gate.hw,
- [CLKID_ENC480P] = &g12a_enc480p.hw,
- [CLKID_RNG1] = &g12a_rng1.hw,
- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
- [CLKID_DMA] = &g12a_dma.hw,
- [CLKID_EFUSE] = &g12a_efuse.hw,
- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
- [CLKID_VPU_0] = &g12a_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
- [CLKID_VPU_1] = &g12a_vpu_1.hw,
- [CLKID_VPU] = &g12a_vpu.hw,
- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
- [CLKID_VAPB] = &g12a_vapb.hw,
- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
- [CLKID_VCLK] = &g12a_vclk.hw,
- [CLKID_VCLK2] = &g12a_vclk2.hw,
- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
- [CLKID_HDMI] = &g12a_hdmi.hw,
- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
- [CLKID_MALI_0] = &g12a_mali_0.hw,
- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
- [CLKID_MALI_1] = &g12a_mali_1.hw,
- [CLKID_MALI] = &g12a_mali.hw,
- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
- [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
- [CLKID_TS_DIV] = &g12a_ts_div.hw,
- [CLKID_TS] = &g12a_ts.hw,
- [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
- [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
- [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
- [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
- [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
- [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
- [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
- [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
- [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
- [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
- [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
- [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
- [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
- [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
- [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
- [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
- [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
- [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
- [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
- [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
- [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
- [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
- [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
- [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
- [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
- [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
- [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
- [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
- [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
- [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
- [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
- [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
- [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
- [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
- [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
-};
-
-static struct clk_hw_onecell_data sm1_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
- [CLKID_CLK81] = &g12a_clk81.hw,
- [CLKID_MPLL0] = &g12a_mpll0.hw,
- [CLKID_MPLL1] = &g12a_mpll1.hw,
- [CLKID_MPLL2] = &g12a_mpll2.hw,
- [CLKID_MPLL3] = &g12a_mpll3.hw,
- [CLKID_DDR] = &g12a_ddr.hw,
- [CLKID_DOS] = &g12a_dos.hw,
- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
- [CLKID_ISA] = &g12a_isa.hw,
- [CLKID_PL301] = &g12a_pl301.hw,
- [CLKID_PERIPHS] = &g12a_periphs.hw,
- [CLKID_SPICC0] = &g12a_spicc_0.hw,
- [CLKID_I2C] = &g12a_i2c.hw,
- [CLKID_SANA] = &g12a_sana.hw,
- [CLKID_SD] = &g12a_sd.hw,
- [CLKID_RNG0] = &g12a_rng0.hw,
- [CLKID_UART0] = &g12a_uart0.hw,
- [CLKID_SPICC1] = &g12a_spicc_1.hw,
- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
- [CLKID_AUDIO] = &g12a_audio.hw,
- [CLKID_ETH] = &g12a_eth_core.hw,
- [CLKID_DEMUX] = &g12a_demux.hw,
- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
- [CLKID_ADC] = &g12a_adc.hw,
- [CLKID_UART1] = &g12a_uart1.hw,
- [CLKID_G2D] = &g12a_g2d.hw,
- [CLKID_RESET] = &g12a_reset.hw,
- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
- [CLKID_PARSER] = &g12a_parser.hw,
- [CLKID_USB] = &g12a_usb_general.hw,
- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
- [CLKID_BT656] = &g12a_bt656.hw,
- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
- [CLKID_UART2] = &g12a_uart2.hw,
- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
- [CLKID_GIC] = &g12a_gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
- [CLKID_IEC958] = &g12a_iec958_gate.hw,
- [CLKID_ENC480P] = &g12a_enc480p.hw,
- [CLKID_RNG1] = &g12a_rng1.hw,
- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
- [CLKID_DMA] = &g12a_dma.hw,
- [CLKID_EFUSE] = &g12a_efuse.hw,
- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
- [CLKID_VPU_0] = &g12a_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
- [CLKID_VPU_1] = &g12a_vpu_1.hw,
- [CLKID_VPU] = &g12a_vpu.hw,
- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
- [CLKID_VAPB] = &g12a_vapb.hw,
- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
- [CLKID_VCLK] = &g12a_vclk.hw,
- [CLKID_VCLK2] = &g12a_vclk2.hw,
- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
- [CLKID_HDMI] = &g12a_hdmi.hw,
- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
- [CLKID_MALI_0] = &g12a_mali_0.hw,
- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
- [CLKID_MALI_1] = &g12a_mali_1.hw,
- [CLKID_MALI] = &g12a_mali.hw,
- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
- [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
- [CLKID_TS_DIV] = &g12a_ts_div.hw,
- [CLKID_TS] = &g12a_ts.hw,
- [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
- [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
- [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
- [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
- [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
- [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
- [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
- [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
- [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
- [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
- [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
- [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
- [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
- [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
- [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
- [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
- [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
- [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
- [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
- [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *g12a_hw_clks[] = {
+ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &g12a_clk81.hw,
+ [CLKID_MPLL0] = &g12a_mpll0.hw,
+ [CLKID_MPLL1] = &g12a_mpll1.hw,
+ [CLKID_MPLL2] = &g12a_mpll2.hw,
+ [CLKID_MPLL3] = &g12a_mpll3.hw,
+ [CLKID_DDR] = &g12a_ddr.hw,
+ [CLKID_DOS] = &g12a_dos.hw,
+ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+ [CLKID_ISA] = &g12a_isa.hw,
+ [CLKID_PL301] = &g12a_pl301.hw,
+ [CLKID_PERIPHS] = &g12a_periphs.hw,
+ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+ [CLKID_I2C] = &g12a_i2c.hw,
+ [CLKID_SANA] = &g12a_sana.hw,
+ [CLKID_SD] = &g12a_sd.hw,
+ [CLKID_RNG0] = &g12a_rng0.hw,
+ [CLKID_UART0] = &g12a_uart0.hw,
+ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+ [CLKID_AUDIO] = &g12a_audio.hw,
+ [CLKID_ETH] = &g12a_eth_core.hw,
+ [CLKID_DEMUX] = &g12a_demux.hw,
+ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+ [CLKID_ADC] = &g12a_adc.hw,
+ [CLKID_UART1] = &g12a_uart1.hw,
+ [CLKID_G2D] = &g12a_g2d.hw,
+ [CLKID_RESET] = &g12a_reset.hw,
+ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+ [CLKID_PARSER] = &g12a_parser.hw,
+ [CLKID_USB] = &g12a_usb_general.hw,
+ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+ [CLKID_BT656] = &g12a_bt656.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+ [CLKID_UART2] = &g12a_uart2.hw,
+ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+ [CLKID_GIC] = &g12a_gic.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+ [CLKID_ENC480P] = &g12a_enc480p.hw,
+ [CLKID_RNG1] = &g12a_rng1.hw,
+ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+ [CLKID_DMA] = &g12a_dma.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
+ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+ [CLKID_VPU] = &g12a_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+ [CLKID_VAPB] = &g12a_vapb.hw,
+ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+ [CLKID_VCLK] = &g12a_vclk.hw,
+ [CLKID_VCLK2] = &g12a_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+ [CLKID_HDMI] = &g12a_hdmi.hw,
+ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+ [CLKID_MALI_0] = &g12a_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+ [CLKID_MALI_1] = &g12a_mali_1.hw,
+ [CLKID_MALI] = &g12a_mali.hw,
+ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+ [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
+ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+ [CLKID_TS] = &g12a_ts.hw,
+ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
+};
+
+static struct clk_hw *g12b_hw_clks[] = {
+ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &g12a_clk81.hw,
+ [CLKID_MPLL0] = &g12a_mpll0.hw,
+ [CLKID_MPLL1] = &g12a_mpll1.hw,
+ [CLKID_MPLL2] = &g12a_mpll2.hw,
+ [CLKID_MPLL3] = &g12a_mpll3.hw,
+ [CLKID_DDR] = &g12a_ddr.hw,
+ [CLKID_DOS] = &g12a_dos.hw,
+ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+ [CLKID_ISA] = &g12a_isa.hw,
+ [CLKID_PL301] = &g12a_pl301.hw,
+ [CLKID_PERIPHS] = &g12a_periphs.hw,
+ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+ [CLKID_I2C] = &g12a_i2c.hw,
+ [CLKID_SANA] = &g12a_sana.hw,
+ [CLKID_SD] = &g12a_sd.hw,
+ [CLKID_RNG0] = &g12a_rng0.hw,
+ [CLKID_UART0] = &g12a_uart0.hw,
+ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+ [CLKID_AUDIO] = &g12a_audio.hw,
+ [CLKID_ETH] = &g12a_eth_core.hw,
+ [CLKID_DEMUX] = &g12a_demux.hw,
+ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+ [CLKID_ADC] = &g12a_adc.hw,
+ [CLKID_UART1] = &g12a_uart1.hw,
+ [CLKID_G2D] = &g12a_g2d.hw,
+ [CLKID_RESET] = &g12a_reset.hw,
+ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+ [CLKID_PARSER] = &g12a_parser.hw,
+ [CLKID_USB] = &g12a_usb_general.hw,
+ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+ [CLKID_BT656] = &g12a_bt656.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+ [CLKID_UART2] = &g12a_uart2.hw,
+ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+ [CLKID_GIC] = &g12a_gic.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+ [CLKID_ENC480P] = &g12a_enc480p.hw,
+ [CLKID_RNG1] = &g12a_rng1.hw,
+ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+ [CLKID_DMA] = &g12a_dma.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
+ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+ [CLKID_VPU] = &g12a_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+ [CLKID_VAPB] = &g12a_vapb.hw,
+ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+ [CLKID_VCLK] = &g12a_vclk.hw,
+ [CLKID_VCLK2] = &g12a_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+ [CLKID_HDMI] = &g12a_hdmi.hw,
+ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+ [CLKID_MALI_0] = &g12a_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+ [CLKID_MALI_1] = &g12a_mali_1.hw,
+ [CLKID_MALI] = &g12a_mali.hw,
+ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+ [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
+ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+ [CLKID_TS] = &g12a_ts.hw,
+ [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
+ [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
+ [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
+ [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
+ [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
+ [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
+ [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
+ [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
+ [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
+ [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
+ [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
+ [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
+ [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
+ [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
+ [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
+ [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
+ [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
+ [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
+ [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
+ [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
+ [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
+ [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
+ [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
+ [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
+ [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
+ [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
+ [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
+ [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
+ [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
+ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
+ [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
+ [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
+ [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
+ [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
+ [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
+};
+
+static struct clk_hw *sm1_hw_clks[] = {
+ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &g12a_clk81.hw,
+ [CLKID_MPLL0] = &g12a_mpll0.hw,
+ [CLKID_MPLL1] = &g12a_mpll1.hw,
+ [CLKID_MPLL2] = &g12a_mpll2.hw,
+ [CLKID_MPLL3] = &g12a_mpll3.hw,
+ [CLKID_DDR] = &g12a_ddr.hw,
+ [CLKID_DOS] = &g12a_dos.hw,
+ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+ [CLKID_ISA] = &g12a_isa.hw,
+ [CLKID_PL301] = &g12a_pl301.hw,
+ [CLKID_PERIPHS] = &g12a_periphs.hw,
+ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+ [CLKID_I2C] = &g12a_i2c.hw,
+ [CLKID_SANA] = &g12a_sana.hw,
+ [CLKID_SD] = &g12a_sd.hw,
+ [CLKID_RNG0] = &g12a_rng0.hw,
+ [CLKID_UART0] = &g12a_uart0.hw,
+ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+ [CLKID_AUDIO] = &g12a_audio.hw,
+ [CLKID_ETH] = &g12a_eth_core.hw,
+ [CLKID_DEMUX] = &g12a_demux.hw,
+ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+ [CLKID_ADC] = &g12a_adc.hw,
+ [CLKID_UART1] = &g12a_uart1.hw,
+ [CLKID_G2D] = &g12a_g2d.hw,
+ [CLKID_RESET] = &g12a_reset.hw,
+ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+ [CLKID_PARSER] = &g12a_parser.hw,
+ [CLKID_USB] = &g12a_usb_general.hw,
+ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+ [CLKID_BT656] = &g12a_bt656.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+ [CLKID_UART2] = &g12a_uart2.hw,
+ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+ [CLKID_GIC] = &g12a_gic.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+ [CLKID_ENC480P] = &g12a_enc480p.hw,
+ [CLKID_RNG1] = &g12a_rng1.hw,
+ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+ [CLKID_DMA] = &g12a_dma.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
+ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+ [CLKID_VPU] = &g12a_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+ [CLKID_VAPB] = &g12a_vapb.hw,
+ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+ [CLKID_VCLK] = &g12a_vclk.hw,
+ [CLKID_VCLK2] = &g12a_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+ [CLKID_HDMI] = &g12a_hdmi.hw,
+ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+ [CLKID_MALI_0] = &g12a_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+ [CLKID_MALI_1] = &g12a_mali_1.hw,
+ [CLKID_MALI] = &g12a_mali.hw,
+ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+ [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
+ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+ [CLKID_TS] = &g12a_ts.hw,
+ [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
+ [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
+ [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
+ [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
+ [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
+ [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
+ [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
+ [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
+ [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
+ [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
+ [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
+ [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
+ [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
+ [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
+ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
+ [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
+ [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
+ [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
+ [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
+ [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
};
/* Convenience table to populate regmap in .probe */
@@ -5274,7 +5262,7 @@ static int meson_g12a_dvfs_setup_common(struct device *dev,
static int meson_g12b_dvfs_setup(struct platform_device *pdev)
{
- struct clk_hw **hws = g12b_hw_onecell_data.hws;
+ struct clk_hw **hws = g12b_hw_clks;
struct device *dev = &pdev->dev;
struct clk *notifier_clk;
struct clk_hw *xtal;
@@ -5351,7 +5339,7 @@ static int meson_g12b_dvfs_setup(struct platform_device *pdev)
static int meson_g12a_dvfs_setup(struct platform_device *pdev)
{
- struct clk_hw **hws = g12a_hw_onecell_data.hws;
+ struct clk_hw **hws = g12a_hw_clks;
struct device *dev = &pdev->dev;
struct clk *notifier_clk;
int ret;
@@ -5413,7 +5401,8 @@ static const struct meson_g12a_data g12a_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &g12a_hw_onecell_data,
+ .hw_clks = g12a_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(g12a_hw_clks),
.init_regs = g12a_init_regs,
.init_count = ARRAY_SIZE(g12a_init_regs),
},
@@ -5424,7 +5413,8 @@ static const struct meson_g12a_data g12b_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &g12b_hw_onecell_data,
+ .hw_clks = g12b_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(g12b_hw_clks),
},
.dvfs_setup = meson_g12b_dvfs_setup,
};
@@ -5433,7 +5423,8 @@ static const struct meson_g12a_data sm1_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &sm1_hw_onecell_data,
+ .hw_clks = sm1_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(sm1_hw_clks),
},
.dvfs_setup = meson_g12a_dvfs_setup,
};
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index a97613df38b3..a70a0cba892b 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -266,8 +266,6 @@
#define CLKID_NNA_CORE_CLK_DIV 266
#define CLKID_MIPI_DSI_PXCLK_DIV 268
-#define NR_CLKS 271
-
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 608e0e8ca49a..4849189cefbc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -2728,428 +2728,420 @@ static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
/* Array of all clocks provided by this provider */
-static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
- [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
- [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
- [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
- [CLKID_CLK81] = &gxbb_clk81.hw,
- [CLKID_MPLL0] = &gxbb_mpll0.hw,
- [CLKID_MPLL1] = &gxbb_mpll1.hw,
- [CLKID_MPLL2] = &gxbb_mpll2.hw,
- [CLKID_DDR] = &gxbb_ddr.hw,
- [CLKID_DOS] = &gxbb_dos.hw,
- [CLKID_ISA] = &gxbb_isa.hw,
- [CLKID_PL301] = &gxbb_pl301.hw,
- [CLKID_PERIPHS] = &gxbb_periphs.hw,
- [CLKID_SPICC] = &gxbb_spicc.hw,
- [CLKID_I2C] = &gxbb_i2c.hw,
- [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
- [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
- [CLKID_RNG0] = &gxbb_rng0.hw,
- [CLKID_UART0] = &gxbb_uart0.hw,
- [CLKID_SDHC] = &gxbb_sdhc.hw,
- [CLKID_STREAM] = &gxbb_stream.hw,
- [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
- [CLKID_SDIO] = &gxbb_sdio.hw,
- [CLKID_ABUF] = &gxbb_abuf.hw,
- [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
- [CLKID_SPI] = &gxbb_spi.hw,
- [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
- [CLKID_ETH] = &gxbb_eth.hw,
- [CLKID_DEMUX] = &gxbb_demux.hw,
- [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
- [CLKID_IEC958] = &gxbb_iec958.hw,
- [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
- [CLKID_AMCLK] = &gxbb_amclk.hw,
- [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
- [CLKID_MIXER] = &gxbb_mixer.hw,
- [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
- [CLKID_ADC] = &gxbb_adc.hw,
- [CLKID_BLKMV] = &gxbb_blkmv.hw,
- [CLKID_AIU] = &gxbb_aiu.hw,
- [CLKID_UART1] = &gxbb_uart1.hw,
- [CLKID_G2D] = &gxbb_g2d.hw,
- [CLKID_USB0] = &gxbb_usb0.hw,
- [CLKID_USB1] = &gxbb_usb1.hw,
- [CLKID_RESET] = &gxbb_reset.hw,
- [CLKID_NAND] = &gxbb_nand.hw,
- [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
- [CLKID_USB] = &gxbb_usb.hw,
- [CLKID_VDIN1] = &gxbb_vdin1.hw,
- [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
- [CLKID_EFUSE] = &gxbb_efuse.hw,
- [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
- [CLKID_DVIN] = &gxbb_dvin.hw,
- [CLKID_UART2] = &gxbb_uart2.hw,
- [CLKID_SANA] = &gxbb_sana.hw,
- [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
- [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
- [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
- [CLKID_ENC480P] = &gxbb_enc480p.hw,
- [CLKID_RNG1] = &gxbb_rng1.hw,
- [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
- [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
- [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
- [CLKID_EDP] = &gxbb_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
- [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
- [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
- [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
- [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
- [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
- [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
- [CLKID_MALI_0] = &gxbb_mali_0.hw,
- [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
- [CLKID_MALI_1] = &gxbb_mali_1.hw,
- [CLKID_MALI] = &gxbb_mali.hw,
- [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
- [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
- [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
- [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
- [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
- [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
- [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
- [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
- [CLKID_VPU_0] = &gxbb_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
- [CLKID_VPU_1] = &gxbb_vpu_1.hw,
- [CLKID_VPU] = &gxbb_vpu.hw,
- [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
- [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
- [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
- [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
- [CLKID_VAPB] = &gxbb_vapb.hw,
- [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
- [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
- [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
- [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
- [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
- [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
- [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
- [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
- [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
- [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
- [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
- [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
- [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
- [CLKID_VCLK] = &gxbb_vclk.hw,
- [CLKID_VCLK2] = &gxbb_vclk2.hw,
- [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
- [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
- [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
- [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
- [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
- [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
- [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
- [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
- [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
- [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
- [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
- [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
- [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
- [CLKID_HDMI] = &gxbb_hdmi.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
-};
-
-static struct clk_hw_onecell_data gxl_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
- [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
- [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
- [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
- [CLKID_CLK81] = &gxbb_clk81.hw,
- [CLKID_MPLL0] = &gxbb_mpll0.hw,
- [CLKID_MPLL1] = &gxbb_mpll1.hw,
- [CLKID_MPLL2] = &gxbb_mpll2.hw,
- [CLKID_DDR] = &gxbb_ddr.hw,
- [CLKID_DOS] = &gxbb_dos.hw,
- [CLKID_ISA] = &gxbb_isa.hw,
- [CLKID_PL301] = &gxbb_pl301.hw,
- [CLKID_PERIPHS] = &gxbb_periphs.hw,
- [CLKID_SPICC] = &gxbb_spicc.hw,
- [CLKID_I2C] = &gxbb_i2c.hw,
- [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
- [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
- [CLKID_RNG0] = &gxbb_rng0.hw,
- [CLKID_UART0] = &gxbb_uart0.hw,
- [CLKID_SDHC] = &gxbb_sdhc.hw,
- [CLKID_STREAM] = &gxbb_stream.hw,
- [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
- [CLKID_SDIO] = &gxbb_sdio.hw,
- [CLKID_ABUF] = &gxbb_abuf.hw,
- [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
- [CLKID_SPI] = &gxbb_spi.hw,
- [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
- [CLKID_ETH] = &gxbb_eth.hw,
- [CLKID_DEMUX] = &gxbb_demux.hw,
- [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
- [CLKID_IEC958] = &gxbb_iec958.hw,
- [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
- [CLKID_AMCLK] = &gxbb_amclk.hw,
- [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
- [CLKID_MIXER] = &gxbb_mixer.hw,
- [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
- [CLKID_ADC] = &gxbb_adc.hw,
- [CLKID_BLKMV] = &gxbb_blkmv.hw,
- [CLKID_AIU] = &gxbb_aiu.hw,
- [CLKID_UART1] = &gxbb_uart1.hw,
- [CLKID_G2D] = &gxbb_g2d.hw,
- [CLKID_USB0] = &gxbb_usb0.hw,
- [CLKID_USB1] = &gxbb_usb1.hw,
- [CLKID_RESET] = &gxbb_reset.hw,
- [CLKID_NAND] = &gxbb_nand.hw,
- [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
- [CLKID_USB] = &gxbb_usb.hw,
- [CLKID_VDIN1] = &gxbb_vdin1.hw,
- [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
- [CLKID_EFUSE] = &gxbb_efuse.hw,
- [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
- [CLKID_DVIN] = &gxbb_dvin.hw,
- [CLKID_UART2] = &gxbb_uart2.hw,
- [CLKID_SANA] = &gxbb_sana.hw,
- [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
- [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
- [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
- [CLKID_ENC480P] = &gxbb_enc480p.hw,
- [CLKID_RNG1] = &gxbb_rng1.hw,
- [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
- [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
- [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
- [CLKID_EDP] = &gxbb_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
- [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
- [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
- [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
- [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
- [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
- [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
- [CLKID_MALI_0] = &gxbb_mali_0.hw,
- [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
- [CLKID_MALI_1] = &gxbb_mali_1.hw,
- [CLKID_MALI] = &gxbb_mali.hw,
- [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
- [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
- [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
- [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
- [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
- [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
- [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
- [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
- [CLKID_VPU_0] = &gxbb_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
- [CLKID_VPU_1] = &gxbb_vpu_1.hw,
- [CLKID_VPU] = &gxbb_vpu.hw,
- [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
- [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
- [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
- [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
- [CLKID_VAPB] = &gxbb_vapb.hw,
- [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
- [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
- [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
- [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
- [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
- [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
- [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
- [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
- [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
- [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
- [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
- [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
- [CLKID_VCLK] = &gxbb_vclk.hw,
- [CLKID_VCLK2] = &gxbb_vclk2.hw,
- [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
- [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
- [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
- [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
- [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
- [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
- [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
- [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
- [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
- [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
- [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
- [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
- [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
- [CLKID_HDMI] = &gxbb_hdmi.hw,
- [CLKID_ACODEC] = &gxl_acodec.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *gxbb_hw_clks[] = {
+ [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
+ [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
+ [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &gxbb_clk81.hw,
+ [CLKID_MPLL0] = &gxbb_mpll0.hw,
+ [CLKID_MPLL1] = &gxbb_mpll1.hw,
+ [CLKID_MPLL2] = &gxbb_mpll2.hw,
+ [CLKID_DDR] = &gxbb_ddr.hw,
+ [CLKID_DOS] = &gxbb_dos.hw,
+ [CLKID_ISA] = &gxbb_isa.hw,
+ [CLKID_PL301] = &gxbb_pl301.hw,
+ [CLKID_PERIPHS] = &gxbb_periphs.hw,
+ [CLKID_SPICC] = &gxbb_spicc.hw,
+ [CLKID_I2C] = &gxbb_i2c.hw,
+ [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
+ [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
+ [CLKID_RNG0] = &gxbb_rng0.hw,
+ [CLKID_UART0] = &gxbb_uart0.hw,
+ [CLKID_SDHC] = &gxbb_sdhc.hw,
+ [CLKID_STREAM] = &gxbb_stream.hw,
+ [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
+ [CLKID_SDIO] = &gxbb_sdio.hw,
+ [CLKID_ABUF] = &gxbb_abuf.hw,
+ [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
+ [CLKID_SPI] = &gxbb_spi.hw,
+ [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
+ [CLKID_ETH] = &gxbb_eth.hw,
+ [CLKID_DEMUX] = &gxbb_demux.hw,
+ [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
+ [CLKID_IEC958] = &gxbb_iec958.hw,
+ [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
+ [CLKID_AMCLK] = &gxbb_amclk.hw,
+ [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
+ [CLKID_MIXER] = &gxbb_mixer.hw,
+ [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
+ [CLKID_ADC] = &gxbb_adc.hw,
+ [CLKID_BLKMV] = &gxbb_blkmv.hw,
+ [CLKID_AIU] = &gxbb_aiu.hw,
+ [CLKID_UART1] = &gxbb_uart1.hw,
+ [CLKID_G2D] = &gxbb_g2d.hw,
+ [CLKID_USB0] = &gxbb_usb0.hw,
+ [CLKID_USB1] = &gxbb_usb1.hw,
+ [CLKID_RESET] = &gxbb_reset.hw,
+ [CLKID_NAND] = &gxbb_nand.hw,
+ [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
+ [CLKID_USB] = &gxbb_usb.hw,
+ [CLKID_VDIN1] = &gxbb_vdin1.hw,
+ [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
+ [CLKID_EFUSE] = &gxbb_efuse.hw,
+ [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
+ [CLKID_DVIN] = &gxbb_dvin.hw,
+ [CLKID_UART2] = &gxbb_uart2.hw,
+ [CLKID_SANA] = &gxbb_sana.hw,
+ [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
+ [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
+ [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
+ [CLKID_ENC480P] = &gxbb_enc480p.hw,
+ [CLKID_RNG1] = &gxbb_rng1.hw,
+ [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
+ [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
+ [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
+ [CLKID_EDP] = &gxbb_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
+ [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
+ [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
+ [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
+ [CLKID_MALI_0] = &gxbb_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
+ [CLKID_MALI_1] = &gxbb_mali_1.hw,
+ [CLKID_MALI] = &gxbb_mali.hw,
+ [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
+ [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
+ [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
+ [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
+ [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
+ [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
+ [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
+ [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
+ [CLKID_VPU_0] = &gxbb_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
+ [CLKID_VPU_1] = &gxbb_vpu_1.hw,
+ [CLKID_VPU] = &gxbb_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
+ [CLKID_VAPB] = &gxbb_vapb.hw,
+ [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
+ [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
+ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
+ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
+ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
+ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
+ [CLKID_VCLK] = &gxbb_vclk.hw,
+ [CLKID_VCLK2] = &gxbb_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
+ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
+ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
+ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
+ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
+ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
+ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
+ [CLKID_HDMI] = &gxbb_hdmi.hw,
+};
+
+static struct clk_hw *gxl_hw_clks[] = {
+ [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
+ [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
+ [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &gxbb_clk81.hw,
+ [CLKID_MPLL0] = &gxbb_mpll0.hw,
+ [CLKID_MPLL1] = &gxbb_mpll1.hw,
+ [CLKID_MPLL2] = &gxbb_mpll2.hw,
+ [CLKID_DDR] = &gxbb_ddr.hw,
+ [CLKID_DOS] = &gxbb_dos.hw,
+ [CLKID_ISA] = &gxbb_isa.hw,
+ [CLKID_PL301] = &gxbb_pl301.hw,
+ [CLKID_PERIPHS] = &gxbb_periphs.hw,
+ [CLKID_SPICC] = &gxbb_spicc.hw,
+ [CLKID_I2C] = &gxbb_i2c.hw,
+ [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
+ [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
+ [CLKID_RNG0] = &gxbb_rng0.hw,
+ [CLKID_UART0] = &gxbb_uart0.hw,
+ [CLKID_SDHC] = &gxbb_sdhc.hw,
+ [CLKID_STREAM] = &gxbb_stream.hw,
+ [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
+ [CLKID_SDIO] = &gxbb_sdio.hw,
+ [CLKID_ABUF] = &gxbb_abuf.hw,
+ [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
+ [CLKID_SPI] = &gxbb_spi.hw,
+ [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
+ [CLKID_ETH] = &gxbb_eth.hw,
+ [CLKID_DEMUX] = &gxbb_demux.hw,
+ [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
+ [CLKID_IEC958] = &gxbb_iec958.hw,
+ [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
+ [CLKID_AMCLK] = &gxbb_amclk.hw,
+ [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
+ [CLKID_MIXER] = &gxbb_mixer.hw,
+ [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
+ [CLKID_ADC] = &gxbb_adc.hw,
+ [CLKID_BLKMV] = &gxbb_blkmv.hw,
+ [CLKID_AIU] = &gxbb_aiu.hw,
+ [CLKID_UART1] = &gxbb_uart1.hw,
+ [CLKID_G2D] = &gxbb_g2d.hw,
+ [CLKID_USB0] = &gxbb_usb0.hw,
+ [CLKID_USB1] = &gxbb_usb1.hw,
+ [CLKID_RESET] = &gxbb_reset.hw,
+ [CLKID_NAND] = &gxbb_nand.hw,
+ [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
+ [CLKID_USB] = &gxbb_usb.hw,
+ [CLKID_VDIN1] = &gxbb_vdin1.hw,
+ [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
+ [CLKID_EFUSE] = &gxbb_efuse.hw,
+ [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
+ [CLKID_DVIN] = &gxbb_dvin.hw,
+ [CLKID_UART2] = &gxbb_uart2.hw,
+ [CLKID_SANA] = &gxbb_sana.hw,
+ [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
+ [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
+ [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
+ [CLKID_ENC480P] = &gxbb_enc480p.hw,
+ [CLKID_RNG1] = &gxbb_rng1.hw,
+ [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
+ [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
+ [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
+ [CLKID_EDP] = &gxbb_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
+ [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
+ [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
+ [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
+ [CLKID_MALI_0] = &gxbb_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
+ [CLKID_MALI_1] = &gxbb_mali_1.hw,
+ [CLKID_MALI] = &gxbb_mali.hw,
+ [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
+ [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
+ [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
+ [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
+ [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
+ [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
+ [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
+ [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
+ [CLKID_VPU_0] = &gxbb_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
+ [CLKID_VPU_1] = &gxbb_vpu_1.hw,
+ [CLKID_VPU] = &gxbb_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
+ [CLKID_VAPB] = &gxbb_vapb.hw,
+ [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
+ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
+ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
+ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
+ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
+ [CLKID_VCLK] = &gxbb_vclk.hw,
+ [CLKID_VCLK2] = &gxbb_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
+ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
+ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
+ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
+ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
+ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
+ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
+ [CLKID_HDMI] = &gxbb_hdmi.hw,
+ [CLKID_ACODEC] = &gxl_acodec.hw,
};
static struct clk_regmap *const gxbb_clk_regmaps[] = {
@@ -3544,13 +3536,15 @@ static struct clk_regmap *const gxl_clk_regmaps[] = {
static const struct meson_eeclkc_data gxbb_clkc_data = {
.regmap_clks = gxbb_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
- .hw_onecell_data = &gxbb_hw_onecell_data,
+ .hw_clks = gxbb_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(gxbb_hw_clks),
};
static const struct meson_eeclkc_data gxl_clkc_data = {
.regmap_clks = gxl_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
- .hw_onecell_data = &gxl_hw_onecell_data,
+ .hw_clks = gxl_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(gxl_hw_clks),
};
static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 1ee8cb7e2f5a..6751cda25986 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -188,8 +188,6 @@
#define CLKID_HDMI_SEL 203
#define CLKID_HDMI_DIV 204
-#define NR_CLKS 207
-
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c
index 0e5e6b57eb20..eb19086b069d 100644
--- a/drivers/clk/meson/meson-eeclk.c
+++ b/drivers/clk/meson/meson-eeclk.c
@@ -14,6 +14,19 @@
#include "clk-regmap.h"
#include "meson-eeclk.h"
+static struct clk_hw *meson_eeclkc_hw_get(struct of_phandle_args *clkspec, void *clk_data)
+{
+ const struct meson_eeclkc_data *data = clk_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->hw_clk_num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hw_clks[idx];
+}
+
int meson_eeclkc_probe(struct platform_device *pdev)
{
const struct meson_eeclkc_data *data;
@@ -43,20 +56,19 @@ int meson_eeclkc_probe(struct platform_device *pdev)
for (i = 0; i < data->regmap_clk_num; i++)
data->regmap_clks[i]->map = map;
- for (i = 0; i < data->hw_onecell_data->num; i++) {
+ for (i = 0; i < data->hw_clk_num; i++) {
/* array might be sparse */
- if (!data->hw_onecell_data->hws[i])
+ if (!data->hw_clks[i])
continue;
- ret = devm_clk_hw_register(dev, data->hw_onecell_data->hws[i]);
+ ret = devm_clk_hw_register(dev, data->hw_clks[i]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- data->hw_onecell_data);
+ return devm_of_clk_add_hw_provider(dev, meson_eeclkc_hw_get, (void *)data);
}
EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eeclk.h
index 77316207bde1..0177fd264f6a 100644
--- a/drivers/clk/meson/meson-eeclk.h
+++ b/drivers/clk/meson/meson-eeclk.h
@@ -17,7 +17,8 @@ struct meson_eeclkc_data {
unsigned int regmap_clk_num;
const struct reg_sequence *init_regs;
unsigned int init_count;
- struct clk_hw_onecell_data *hw_onecell_data;
+ struct clk_hw **hw_clks;
+ unsigned int hw_clk_num;
};
int meson_eeclkc_probe(struct platform_device *pdev);
--
2.34.1
