Re: [PATCH v2 2/6] arm64: zynqmp: Fix usb node drive strength and slew rate

Michal Simek <monstr@xxxxxxxxx> · Mon, 5 Jun 2023 13:15:51 +0200

On 5/22/23 16:59, Michal Simek wrote:
From: Ashok Reddy Soma <ashok.reddy.soma@xxxxxxxxxx>

As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb group pins.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xxxxxxxxxx>
Signed-off-by: Michal Simek <michal.simek@xxxxxxx>
---

(no changes since v1)

c&p more explanation from v1 version.

In design tools all inputs pins are setup like described by default. That's
why it could suggest that there is no need to describe default
configuration in DT. But all MIOs can be used as GPIOs where pinctrl can
change their default values to something else. That's why setting up
default values is to be safe even for input pins. I don't know HW details
to that extend but that values can also change input behavior that's why
having default is not a bad idea.

---
  .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso |  8 ++++++--
  .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso |  8 ++++++--
  .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts     |  8 ++++++--
  .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts     |  8 ++++++--
  arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts   | 13 ++++++++++---
  arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts   |  5 ++++-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts   |  6 ++++--
  arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts   |  6 ++++--
  arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts   |  5 ++++-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts   |  5 ++++-
  10 files changed, 54 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
index 669fe6084f3f..603839c82599 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
@@ -2,7 +2,8 @@
  /*
   * dts file for KV260 revA Carrier Card
   *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * SD level shifter:
   * "A" - A01 board un-modified (NXP)
@@ -265,19 +266,22 @@ mux {
  	pinctrl_usb0_default: usb0-default {
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			"MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  
  		mux {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
index 7886a19139ee..a91d09e7da4b 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
@@ -2,7 +2,8 @@
  /*
   * dts file for KV260 revA Carrier Card
   *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <michal.simek@xxxxxxx>
   */
@@ -248,19 +249,22 @@ mux {
  	pinctrl_usb0_default: usb0-default {
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			"MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  
  		mux {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
index 1a7995ee62ce..af3331c133ad 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <michal.simek@xxxxxxx>
   */
@@ -187,19 +188,22 @@ mux {
  
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
index 869b733a0634..6503f4985f8d 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP zc1751-xm016-dc2
   *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <michal.simek@xxxxxxx>
   */
@@ -281,19 +282,22 @@ mux {
  
  		conf {
  			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO64", "MIO65", "MIO67";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
  			       "MIO72", "MIO73", "MIO74", "MIO75";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
index 544801814bd5..44d1f351bb75 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU100 revC
   *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <michal.simek@xxxxxxx>
   * Nathalie Chan King Choy
@@ -432,19 +433,22 @@ mux {
  
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  
@@ -456,19 +460,22 @@ mux {
  
  		conf {
  			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO64", "MIO65", "MIO67";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
  			       "MIO72", "MIO73", "MIO74", "MIO75";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  };
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index f36353a51863..a074d8e2b86d 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -783,19 +783,22 @@ mux {
  
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index 3fd47725c2c8..91c9b77f6b1f 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -410,20 +410,22 @@ mux {
  
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  };
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
index 4f6429caecff..954044d9899f 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
@@ -422,20 +422,22 @@ mux {
  
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  };
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 8c3fa3fe28d5..ab5e34b43642 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -794,19 +794,22 @@ mux {
  
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index 0d9b6081dff6..f31365a14f73 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -660,19 +660,22 @@ mux {
  
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
  
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
  
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  

Applied.
M

--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs







