* Udit Kumar <u-kumar1@xxxxxx> [230601 09:38]: > There are timer IO pads in the MCU domain, and in the MAIN domain. These > pads can be muxed for the related timers. > > There are timer IO control registers for input and output. The registers > for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control > the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and > CTRLMMR_MCU_TIMERIO*_CTRL the output. > > The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control > Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the > CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". > > For chaining timers, the timer IO control registers also have a CASCADE_EN > input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit > muxes the previous timer output, or possibly and external TIMER_IO pad > source, to the input clock of the selected timer instance for odd numered > timers. For the even numbered timers, the CASCADE_EN bit does not do > anything. The timer cascade input routing options are shown in TRM > "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the > driver support for timer cascading should be likely be handled via the > clock framework. > > The MCU timer controls are also marked as reserved for > usage by the MCU firmware. Reviewed-by: Tony Lindgren <tony@xxxxxxxxxxx>
