On 31/05/23 19:37, Miquel Raynal wrote:
> Hi Chris,
>
> chris.packham@xxxxxxxxxxxxxxxxxxx wrote on Wed, 31 May 2023 14:58:47
> +1200:
>
>> Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only
>> supports SDR modes up to 3.
> Strange!
Yeah I'm a bit surprised too. They only recently updated the datasheet
to say it supported mode 3 so I think maybe they're qualifying things as
they go.
> But alright, I'm okay with the series.
>
> I'll put it aside waiting for all binding changes to be acked (yaml
> conversion series + this one) and then I'll apply everything.
>
>> Marvell's SDK includes some predefined values for the ndtr registers.
>> These haven't been incorporated as the existing code seems to get good
>> values based on measurements taken with an oscilloscope.
> Good :)
>
> By the way did you sort the timings question on 8k?
Yes with those two patches you've already applied the 8k seems good as
far as I'm concerned.
>> Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
>> ---
>> drivers/mtd/nand/raw/Kconfig | 2 +-
>> drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++
>> 2 files changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index b523354dfb00..0f4cbb497010 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL
>> including:
>> - PXA3xx processors (NFCv1)
>> - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
>> - - 64-bit Aramda platforms (7k, 8k) (NFCv2)
>> + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
>>
>> config MTD_NAND_SLC_LPC32XX
>> tristate "NXP LPC32xx SLC NAND controller"
>> diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
>> index 30c15e4e1cc0..b9a8dd324211 100644
>> --- a/drivers/mtd/nand/raw/marvell_nand.c
>> +++ b/drivers/mtd/nand/raw/marvell_nand.c
>> @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip
>> * BCH error detection and correction algorithm,
>> * NDCB3 register has been added
>> * @use_dma: Use dma for data transfers
>> + * @max_mode_number: Maximum timing mode supported by the controller
>> */
>> struct marvell_nfc_caps {
>> unsigned int max_cs_nb;
>> @@ -383,6 +384,7 @@ struct marvell_nfc_caps {
>> bool legacy_of_bindings;
>> bool is_nfcv2;
>> bool use_dma;
>> + unsigned int max_mode_number;
>> };
>>
>> /**
>> @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
>> if (IS_ERR(sdr))
>> return PTR_ERR(sdr);
>>
>> + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode)
>> + return -EOPNOTSUPP;
>> +
>> /*
>> * SDR timings are given in pico-seconds while NFC timings must be
>> * expressed in NAND controller clock cycles, which is half of the
>> @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = {
>> .is_nfcv2 = true,
>> };
>>
>> +static const struct marvell_nfc_caps marvell_ac5_caps = {
>> + .max_cs_nb = 2,
>> + .max_rb_nb = 1,
>> + .is_nfcv2 = true,
>> + .max_mode_number = 3,
>> +};
>> +
>> static const struct marvell_nfc_caps marvell_armada370_nfc_caps = {
>> .max_cs_nb = 4,
>> .max_rb_nb = 2,
>> @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = {
>> .compatible = "marvell,armada-8k-nand-controller",
>> .data = &marvell_armada_8k_nfc_caps,
>> },
>> + {
>> + .compatible = "marvell,ac5-nand-controller",
>> + .data = &marvell_ac5_caps,
>> + },
>> {
>> .compatible = "marvell,armada370-nand-controller",
>> .data = &marvell_armada370_nfc_caps,
>
> Thanks,
> Miquèl
