On 5/19/2023 11:01 PM, Konrad Dybcio wrote:
On 19.05.2023 12:31, Poovendhan Selvaraj wrote:From: POOVENDHAN SELVARAJ <quic_poovendh@xxxxxxxxxxx> Add the initial device tree support for the Reference Design Platform (RDP) 454 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR and SMPA1 regulator node. Signed-off-by: Poovendhan Selvaraj <quic_poovendh@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 92 +++++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7b5466395f46..834e790bec90 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts new file mode 100644 index 000000000000..b3e853a9cc94 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP454 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9"; + compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* In AL02-C9, the max supported CPU Freq is 1.5 GHz. Disabling frequencies beyond 1.5GHz*/In -> On GHz*/ -> GHz */ Disabling -> Disable
Okay. Will address them in next spin
Can this not be determined based on fuse values?
Yes...That should be possible.Will then drop the below cpu_opp_table entries and post a separate series for the same.
+&cpu_opp_table { + opp-1800000000 { + opp-supported-hw = <0>; + }; + + opp-2208000000 { + opp-supported-hw = <0>; + }; +}; + +/* Disable IPQ9574 integrated radio's reserved memory */? Konrad
sorry, will drop it as it got added by mistake. Regards, Poovendhan S
+&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +};
