Hi Krzysztof and Dmitry, On Wed, May 17, 2023 at 3:33 PM Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> wrote: [...] > + clocks: > + items: > + - description: input fixed pll div2 > + - description: input fixed pll div3 > + - description: input fixed pll div5 > + - description: input fixed pll div7 > + - description: input hifi pll > + - description: input oscillator (usually at 24MHz) > + > + clock-names: > + items: > + - const: fclk_div2 > + - const: fclk_div3 > + - const: fclk_div5 > + - const: fclk_div7 > + - const: hifi_pll > + - const: xtal This IP block has at least one additional input called "sys_pll_div16". My understanding is that the "sys_pll_div16" clock is generated by the CPU clock controller. Support for the CPU clock controller (dt-bindings and a driver) will be added at a later time by Dmitry. How can we manage incrementally implementing the clock controllers? >From a hardware perspective the "sys_pll_div16" input is mandatory. How to manage this in the .dts patches then (for example: does this mean that Dmitry can only add the clock controller to the .dts when all clock controller bindings have been implemented - or is there another way)? Best regards, Martin
